We report an SRAM with a 90% reduction of active-leakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells, the wordline voltage is controlled so that it is always lower than the supply voltage in the proposed SRAM, with a self-alignment timing generator. The additional area overhead of the timing generator is 3.5%.

Leakage power is predicted to become dominant in the total operation power as the transistor technology gets advanced. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125, is facing at difficulties such as throughput degradation or thermal runaway due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel approach to make use of an enable signal of a gated-clock technique for reducing active leakage power. A sleep transistor is provided between combinational logic circuits and the ground, and is controlled by the enable signal. When state transitions do not occur in Finite-State-Machines (FSM's), the enable signal becomes low and the state flip-flops keep the data. At the same time, the sleep transistor is turned off so that combinational logic gates are electrically disconnected from the ground to reduce leakage. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60% in 0.18 µm technology. The total power was reduced by 20% at the maximum at 125. It was also found that performance degradation was tolerable for burn-in testing.