A surface extraction algorithm with NURBS has been developed for the mesh generation from the scattered data after a cell-based simulation. The triangulation of a surface is initiated with a step of describing the geometry along the polygonal boundary with multiple points. In this work, an NURBS surface can be generated with scattered data for each polygonal surface by employing a multilevel B-spline surface approximation. The NURBS mesh in accordance with our algorithm excellently represents the surface evolution of the topography on the wafer. A dynamically allocated topography model, so-called cell advancing model, is proposed to resolve an extensive memory requirement for the numerical simulation of a complicated structure on the wafer. A concave cylindrical DRAM cell capacitor was chosen to test the capability of our model. A set of capacitance present in the cell capacitor and interconnects was calculated with three-dimensional tetrahedral meshes generated from the NURBS surface on CRAY T3E supercomputer. A total of 5,475,600 (130 156 270) cells was employed for the simulation of semiconductor regions comprising four DRAM cell capacitors with a dimension of 1.3 µm 1.56 µm 2.7 µm . The size of the required memory is about 22 Mbytes and the simulation time is 64,082 seconds. The number of nodes for the FEM calculation was 70,078 with 395,064 tetrahedrons.

After a brief discussion of the demands in meshing for semiconductor process and device simulation, we present a three-dimensional Delaunay refinement technique combined with a modified advancing front algorithm.