We introduce new computer algorithm of multiple alignment as an application of "Simulated Annealing" method. Simulated Annealing has been applied to some combinational optimization problems such as travelling salesman problem. After giving short mathematical explanation of this method, we construct genetic distance and matrix corresponding to the object function in the annealing theory for the multiple alignment. Our method is better than other alignment in the sense that we obtain a result having a smaller value for the genetic distance. We discuss further development along on new method.

This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

By close analogy of annealing for solids, we devise a new algorithm, called APS, for the time evolution of both the state and the synapses of the Hopfield's neural network. Through constrainedly random perturbation of the synapses of the network, the evolution of the state will ignore the tremendous number of small minima and reach a good minimum. The synapses resemble the microstructure of a network. This new algorithm anneals the microstructure of the network through a thermal controlled process. And the algorithm allows us to obtain a good minimum of the Hopfield's model efficiently. We show the potential of this approach for optimization problems by applying it to the will-known traveling salesman problem. The performance of this new algorithm has been supported by many computer simulations.