Template learning has potential application in several areas of Cellular Neural Network research, including texture recognition, pattern detection and so on. In this letter, a recently-developed algorithm called Adaptive Simulated Annealing is investigated for learning CNN templates, as a superior alternative to the Genetic Algorithm.

The post-annealing process has been investigated for (Ba, Sr)TiO3 [BST] thin films employed as a capacitor dielectric in 1 Gbit dynamic random access memories (DRAMs). The effects of post-annealing on morphology, crystallinity, and dielectric properties were examined for thin film capacitors with BST prepared on Pt electrodes by liquid source chemical vapor deposition (CVD). The direct annealing of BST capacitors caused a roughening in surface morphology of the upper Pt electrodes and BST films. However, the post-annealing of capacitors with a silicon dioxide passivation layer was found to cause little change in surface morphology of Pt and BST, and also no significant deterioration in leakage current. The improvement in crystallinity of BST films through post-annealing was confirmed at a temperature in the range 700-850 by X-ray diffraction (XRD) and transmission electron microscope (TEM). Moreover, the post-annealing experiments for BST films with different compositions showed that the post-annealing greatly increases the dielectric constant of BST films having approximately stoichiometric composition. The leakage and breakdown properties of BST films were also examined, indicating that excess Ti ions result in an increase of the turn-on voltage and the breakdown time. Based on these investigations, the electrical properties of dielectric constant ε 260, equivalent silicon dioxide thickness teq 0. 44 nm, and leakage current JL110-7 A/cm2 at 1. 9 V were successfully obtained for stoichiometric 30-nm-thick BST films post-annealed at 750. Hence, it can be concluded that the post-annealing is a promising technique to enhance the applicability of CVD-deposited BST films with conformal coverage to memory cell capacitors of 1 Gbit DRAMs.

In recently year, the analysis of power management becomes more important. It is difficult to obtain the maximum power because this is NP-complete. For an n-input circuit, there are 22n different input patterns to be considered. There are two major methods for this problem. First method is to generate input patterns to obtain the maximal power by simulating these generated patterns. This method is called pattern based. The other one uses probability method to estimate the power density of each node of a circuit to calculate the maximal power. In this paper, we use a pattern based method to estimate the maximal power. This method is better than that of probability for the simulation of power activity. In practical applications, these generated patterns can be applied and observe the activity of a circuit. These simulated data can be used to examined the critical paths for performance optimization. A simulated annealing algorithm is proposed to search input patterns for maximum power. Firstly, it transforms this problem into an optimization problem to adapt the simulated annealing method. In this method, there are three strategies for generating the next input patterns, called neighborhood. In the first strategy, it generates the next input pattern by changing the status of all input nodes. In the second strategy, some input nodes are selected and changed randomly.

Based on a new search strategy using circuit simulation and simulated annealing with local search, a design tool is proposed to automate design or tuning process for CMOS operational amplifiers. A special-purpose circuit simulator and some heuristics are used to accomplish the design within reasonable time. For arbitrary circuit topology and specifications, the discrete optimization of cost function is performed by global and local search. Through the comparision of design results and the design of a low-power high-speed CMOS operational amplifier usable in 10-b 25-MHz pipelined A/D converters, it has been demonstrated that this tool can be used for designing high-performance operational amplifiers with less design knowledge and effort.

A series of CoxAg1-x (0x100at.%) granular films were prepared using the ion-beam cosputtering technique at different substrate temperatures. Systematic investigations have been carried out on the giant magnetoresistance (GMR) effect and characterization of microstructures of these samples. The magnetoresistance ratio depends strongly on cobalt concentration, substrate temperature, and annealing treatment. The optimal value of GMR was observed in Co22Ag78 sample prepared at the temperature of 300 K. Microstructures of as-deposited and annealed samples were characterized by structural analyses. For Co22Ag78 sample, real-time in situ observation by TEM together with FMR spectra indicates that the size and shape of cobalt granules evolve primarily along the film plane during annealing. The results of FMR also provide that the cobalt granules remain single-domain particles after annealing at temperatures up to 700 K.

This paper reviews the structure and electrical properties of high-quality Internal Thermal OXidation (ITOX)-processed low-dose Separation by IMplanted OXygen (SIMOX) wafers. The ITOX SIMOX process consists of three steps: low-dose oxygen implantation, high-temperature annealing, and high-temperature oxidation. The low dose makes possible a high-throughput production of SIMOX wafers. The high-temperature annealing provides a continuous buried oxide layer and reduces the dislocation density in the top silicon layer. The subsequent high-temperature oxidation thickens the buried oxide layer without any additional oxygen implantation, thus improving its electrical properties. The ITOX mechanism is also described. It is concluded that the ITOX SIMOX wafers are very useful for fabricating ULSIs.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

The resistive-fuse network for early vision was studied using circuit simulation to clarify the potential of implementation with resonant tunneling diodes (RTDs). To over-come the fundamental problem of the RTD network, i.e., the RTDs cannot perform simulated annealing (SA), pseudo SAs were proposed. These methods are based on the time-variation of the input signal strength, and are found to be effective in restoring images. A resistive-fuse network is shown to be one of the most promising applications of RTDs.

In this paper, quantization method which can keep the phase and gain characteristics of a reference filter is proposed. The proposed method uses a genetic algorithm and a simulated annealing algorithm. The objective function used in this method is described with two kinds of weighting functions for identifying the phase and gain characteristics respectively. Therefore, the quantization accuracy on the gain characteristic is independent of the accuracy on the phase characteristic. Further, the proposed algorithm can be applied to any types of filters, because the chromosome expresses only their coefficients values. The efficiency of the proposed algorithm is verified by some experiments.

The mean field theory has been recognized as offering an efficient computational framework in solving discrete optimization problems by neural networks. This paper gives a formulation based on the information geometry to the mean field theory, and makes clear from the information-theoretic point of view the meaning of the mean field theory as a method of approximating a given probability distribution. The geometrical interpretation of the phase transition observed in the mean field annealing is shown on the basis of this formulation. The discussion of the standard mean field theory is extended to introduce a more general computational framework, which we call the generalized mean field theory.

This paper proposes a new block coded quadrature amplitude modulation (BC-QAM) scheme, which is designed by an optimization technique based on simulated annealing. Simulated annealing is an effective nonlinear optimization technique and can be applied to both the discrete and the continuous optimization problems. In this paper, the simulated annealing technique is used to design the optimum BC-QAM signal, which minimizes the upper bound on the bit error rate (BER) in a Rayleigh fading channel. The computer simulation shows that the proposed BC-QAM can improve the BER performance. This paper also proposes a simplified design method to reduce the number of variables to be optimized. The proposed simplified method optimizes the in-phase and quadrature components of the BC-QAM signal separately. The computer simulation also shows that the BC-QAM designed by the simplified method gives little degradation on the BER performance, although the simplified method can significantly reduce the number of optimization variables.

The most creative tasks in synthesizing pipelined data paths executing software descriptions are determinations of latency and stage of pipeline, operation scheduling and hardware allocation. They are interrelated closely and depend on each other; thus finding its optimal solution has been a hard problem so far. By using simulated annealing methodology, these three tasks can be formulated as a three dimensional placement problem of operations in stage, time step and functional units space. This paper presents an efficient method based on simulated annealing to provide excellent solutions to the problem of not only the determinations of latency and stage of pipeline, operation scheduling and hardware allocation simultaneously, but also the pipelined data path synthesis under the constraints of performance or hardware cost. It is able to find a near optimal latency and stage of pipeline, an operation schedule and a hardware allocation in a reasonable time, while effectively exploring the existing tradeoffs in the design space.

A novel adaptive pitch-synchronous analysis method is proposed to estimate simultaneously vocal tract (formant/antiformant) and voice source parameters from speech waveforms. We use the parametric Rosenberg-Klatt (RK) model to generate a glottal waveform and an autoregressive-exogenous (ARX) model to represent voiced speech production process. The Kalman filter algorithm is used to estimate the formant/antiformant parameters from the coefficient of the ARX model, and the simulated annealing method is employed as a nonlinear optimization approach to estimate the voice source parameters. The two approaches work together in a system identification procedure to find the best set of the parameters of both the models. The new method has been compared using synthetic speech with some other approaches in terms of accuracy of estimated parameter values and has been proved to be superior. We also show that the proposed method can estimate accurately the parameters from natural speech sounds. A major application of the analysis method lies in a concatenative formant synthesizer which allows us to make flexible control of voice quality of synthetic speech.

In this paper, we present a method for extracting the Japanese printed characters from unformatted document images. This research takes into account the multiple general features specific to the Japanese printed characters. In our method, these features are thought of as the constraints for the regions to be extracted within the constraint satisfaction approach. This is achieved by minimizing a constraint function estimating quantitative satisfaction of the features. Our method is applicable to all kinds of the Japanese documents because it is no need of a priori knowledge about the document layout. We have favorable experimental results for the effectiveness of this method.

We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.

Recently, high-dose implantation and low temperature annealing have become one of the key techniques in shallow junction formation. To fabricate shallow junction in quarter-micron CMOS VLSIs, it is well known being important to evaluate the transient enhanced diffusion (TED) of implanted dopants at low temperature furnace annealing, which is caused by the damages of implantation. We have newly studied the TED phenomena by a compact empirical method. This approach has merits of simplicity and better physical intuition, because we can use only minimal parameters to describe the TED phenomena. The other purpose of this work is to evaluate two-dimensional transient enhanced diffusion focusing on phosphorus implant and furnace annealing. Firstly, we defined effective diffusivity of the TED and determined extraction procedure of the model parameters. Number of the TED model parameters is minimized to two, which describe effective enhanced diffusivity and its activation energy. The parameters have been extracted from SIMS profile data obtained from samples which range 1013-31015 cm-2 and 850-950 for phosphorus implanted dose and annealing temperature, respectively. Simulation results with the extracted transient enhanced diffusion parameters show good agreements well with the SIMS data within 2% RMS-error. Critical doses for phosphorus enhanced diffusion have been determined in 950 annealing condition. No transient enhanced diffusion is observed at 950 under the implant dose of 11013 cm-2. Also the transient enhanced diffusivity is leveled off over the dose of 11014 cm-2. It is seen that the critical dose in TED phenomena might be temperature dependent to a certain extent. We have also verified that two-dimensional effect of the TED phenomena experimentally. Two-dimensional phosphorus n- layer is chosen to verify the simulation. It was concluded that the TED has isotropic nature in phosphorus n- diffusion formation.

An analog approach alternative to the Hopfield method is presented for solving constrained combinatorial optimization problems. In this new method, a saddle point of a Lagrangian function is searched using a constrained dynamical system with the aid of an appropriate transformation of variables. This method always gives feasible solutions in contrast to the Hopfield scheme which often outputs infeasible solutions. The convergence of the method is proved theoretically and some effective schemes are recommended for eliminating some variables for the case we resort to numerical simulation. An analog electronic circuit is devised which implements this method. This circuit requires fewer wirings than the Hopfield networks. Furthermore this circuit dissipates little electrical power owing to subthreshold operation of MOS transistors. An annealing process, if desired, can be performed easily by gradual increase in resistance of linear resistors in contrast to the Hopfield circuit which requires the variation in the gain of amplifiers. The objective function called an energy is ensured theoretically to decrease throughout the annealing process.

The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.

Self-aligned aluminum-gate MOSFET's have been successfully fabricated by employing ultraclean ion implantation technology. The use of ultra high vacuum ion implanter and the suppression of high-energy ion-beam-induced metal sputter contamination have enabled us to form ultra-shallow low-leakage pn junctions by furnace annealing at a temperature as low as 450. The fabricated aluminum-gate MOSFET's have exhibited good electrical characteristics, thus demonstrating a large potential for application to realizing ultra-high-speed integrated circuits.

The a-Si films deposited on quartz substrates were crystallized by lateral sweep annealing in steep temperature gradient using a gas burner. Random nucleation in amorphous region was effectively suppressed in the temperature gradient, so lateral solid phase epitaxial growth from crystallites generated at the initial stage of lateral sweep annealing spread over 100 µm. Their crystallographic orientations were mostly (100).