Power line communication (PLC) provides a flexible-access, wide-distribution, and low-cost communication solution for distribution network services. However, the PLC self-organizing networking in distribution network faces several challenges such as diversified data transmission requirements guarantee, the contradiction between long-term constraints and short-term optimization, and the uncertainty of global information. To address these challenges, we propose a backpressure learning-based data transmission reliability-aware self-organizing networking algorithm to minimize the weighted sum of node data backlogs under the long-term transmission reliability constraint. Specifically, the minimization problem is transformed by the Lyapunov optimization and backpressure algorithm. Finally, we propose a backpressure and data transmission reliability-aware state-action-reward-state-action (SARSA)-based self-organizing networking strategy to realize the PLC networking optimization. Simulation results demonstrate that the proposed algorithm has superior performances of data backlogs and transmission reliability.

In communication networks, congestion control, routing, and multiple access schemes for scheduling transmissions are typically regulated by distributed algorithms. Engineers designed these algorithms using clever heuristics that they refined in the light of simulation results and experiments. Over the last two decades, a deeper understanding of these algorithms emerged through the work of researchers. This understanding has a real potential for improving the design of protocols for data centers, cloud computing, and even wireless networks. Since protocols tend to be standardized by engineers, it is important that they become familiar with the insights that emerged in research. We hope that this paper might appeal to practitioners and make the research results intuitive and useful. The methods that the paper describes may be useful for many other resource allocation problems such as in call centers, manufacturing lines, hospitals and the service industry.

Input and output queueing nonblocking switch with feed-back loop is proposed in order to reduce the system delay. It has b head of the line (HOL)'s and b output ports feed-backed into the HOL's of feed-back loop. The cell which receives backpressure over threshold is switched and enters one of these HOL's through a feed-back loop. It provides the cell, which should wait behind the HOL of input queue until the cell in that HOL is served, with opportunity to be served immediately by vacating the HOL of the input queue. We obtain the mean system delay and consider the effect of the size of b by computer simulation. As the results, it is shown that proposed switch with appropriate size of b can reduce the system delay compared to the conventional switch.

Input and output queueing two stage ATM switch model which is effective under variable hot-spot traffic is proposed. In order to prevent the degradation of performance due to hot-spot traffic, the hot-spot route is added in which cells destined to the hot-spot port bypass. The switch applies the backpressure mode basically. When the switch judges that the hot-spot port exists, it routes cells destined there to the hot-spot route and applies the queue loss mode on them. We evaluate both the cell loss probability and the mean system delay under the nonuniform traffic with variable hot-spot port by computer simulation. As the results, it is shown that our proposed switch can achieve better switching performance than those of conventional switches under variable traffic condition.

This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.