This paper proposes a technique that increases the lifetime of large scale integration (LSI) devices. As semiconductor technology improves at miniaturizing transistors, aging effects due to bias temperature instability (BTI) seriously affects their lifetime. BTI increases the threshold voltage of transistors thereby also increasing the delay of an electronics device, resulting in failures due to timing violations. To compensate for aging-induced timing violations, we exploit configurable approximate computing. Assuming that target circuits have exact and approximate modes, they are configured for the approximate mode if an aging sensor predicts violations. Experiments using an example circuit revealed an increase in its lifetime to >10 years.

The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (VG=VD). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.

Ternary content addressable memory (TCAM), which can store 0, 1, or X in its cells, is widely used to store routing tables in network routers. Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI), which increase Vth and degrade transistor switching speed, have become major reliability challenges. This study analyzes the signal probability of routing tables. The results show that many cells retain static stress and suffer significant degradation caused by NBTI and PBTI effects. The bit flipping technique is improved and proactive power gating recovery is proposed to mitigate NBTI and PBTI effects. In order to maintain the functionality of TCAM after bit flipping, a novel TCAM cell design is proposed. Simulation results show that compared to the original architecture, the bit flipping technique improves read static noise margin (SNM) for data and mask cells by 16.84% and 29.94%, respectively, and reduces search time degradation by 12.95%. The power gating technique improves read SNM for data and mask cells by 12.31% and 20.92%, respectively, and reduces search time degradation by 17.57%. When both techniques are used, read SNM for data and mask cells is improved by 17.74% and 30.53%, respectively, and search time degradation is reduced by 21.01%.

In this paper, negative bias temperature instability (NBTI) reliability of pFETs is analyzed under the post-fabrication SRAM self-improvement scheme that we have developed recently, where cell stability is self-improved by simply applying high stress voltage to supply voltage terminal (VDD) of SRAM cells. It is newly found that there is no significant difference in both threshold voltage and drain current degradation by NBTI stress between fresh PFETs and PFETs after self-improvement scheme application, indicating that the self-improvement scheme has no critical reliability problem.

Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our NBTI model. The simulation results show that: 1) the execution of a low temperature task can decrease ΔVth due to NBTI by 24.5%; 2) switching to standby mode can decrease ΔVth by 52.3%; 3) for ISCAS85 benchmark circuits, the delay degradation can decrease significantly if the circuit execute low temperature task or switch to standby mode; 4) we have also observed the execution time's ratio of different tasks and the ratio of active to standby time both have a considerable impact on NBTI effect.