Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs

Wen-Teng CHANG; Shih-Wei LIN; Min-Cheng CHEN; Wen-Kuan YEH

doi:10.1587/transele.2018FUP0006

IEICE TRANSACTIONS on Electronics

Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs

Wen-Teng CHANG, Shih-Wei LIN, Min-Cheng CHEN, Wen-Kuan YEH

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The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (V_G=V_D). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.

Publication: IEICE TRANSACTIONS on Electronics Vol.E102-C No.6 pp.429-434

Publication Date: 2019/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.2018FUP0006

Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)

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Authors

Wen-Teng CHANG
  National University of Kaohsiung
Shih-Wei LIN
  National University of Kaohsiung
Min-Cheng CHEN
  National Nano Device Laboratories
Wen-Kuan YEH
  National Nano Device Laboratories

Keyword

FinFET, channel orientation, surface orientation, mechanical stress, strain engineering, bias temperature instability, hot carrier injection

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Wen-Teng CHANG, Shih-Wei LIN, Min-Cheng CHEN, Wen-Kuan YEH, "Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs" in IEICE TRANSACTIONS on Electronics, vol. E102-C, no. 6, pp. 429-434, June 2019, doi: 10.1587/transele.2018FUP0006.
Abstract: The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (V_G=V_D). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018FUP0006/_p

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@ARTICLE{e102-c_6_429,
author={Wen-Teng CHANG, Shih-Wei LIN, Min-Cheng CHEN, Wen-Kuan YEH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs},
year={2019},
volume={E102-C},
number={6},
pages={429-434},
abstract={The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (V_G=V_D). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.},
keywords={},
doi={10.1587/transele.2018FUP0006},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 429
EP - 434
AU - Wen-Teng CHANG
AU - Shih-Wei LIN
AU - Min-Cheng CHEN
AU - Wen-Kuan YEH
PY - 2019
DO - 10.1587/transele.2018FUP0006
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2019
AB - The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (V_G=V_D). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.
ER -

IEICE TRANSACTIONS on Electronics