Modern processors use Branch Target Buffer (BTB)[1] to relax control dependence. Unfortunately, the energy consumption of the BTB is high. In order to effectively fetch instructions, it is necessary to perform a branch prediction at the fetch stage, regardless of whether the fetched instruction is a branch or a nonbranch. Therefore, the number of accesses to the BTB is large, and the energy consumption of the BTB is high. However, accesses from nonbranches to the BTB waste energy. In this paper, we focus on accesses from nonbranches to the BTB, which we call useless accesses from a viewpoint of power. For reducing energy consumption without performance loss, we present a method that reduces useless accesses by using information that indicates whether a fetched instruction is a branch or not. To realize the above approach, we propose a branch bit called B-Bit. A B-Bit is associated with an instruction and indicates whether it is a branch or not. A B-Bit is available at the beginning of the fetch stage. If a B-Bit is “1” signifying a branch, the BTB is accessed. If a B-Bit is “0” signifying a nonbranch, the BTB is not accessed. The experimental results show that the total energy consumption can be reduced by 54.3% without performance loss.

Modern micro-architectures employ superscalar techniques to enhance system performance. Since the superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amount speculative executions. There are cases that multiple branches are often encountered in one cycle. And in practical implementation this would cause serious problem while there are variable number of instruction addresses that look up the Branch Target Buffer simultaneously. In this paper, we propose a Range Associative Branch Target Buffer (RABTB) that can recognize and predict multiple branches in the same instruction cache line for a wide-issue micro-architecture. Several configurations of the RABTB are simulated and compared using the SPECint95 benchmarks. We show that with a reasonable size of prediction scope, branch prediction can be improved by supporting multiple / up to 8 branch predictions in one cache line in one cycle. Our simulation results show that the optimal RABTB should be 2048 entry, 8-column range-associate and 8-entry modified ring buffer architecture using PAs prediction algorithm. It has an average 5.2 IPC_f and branch penalty per branch of 0.54 cycles. This is almost two times better than a mechanism that makes prediction only on the first encountered branch.