This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.

Time-interleaving is an efficient approach to increase the effective sampling rate of the ΣΔ modulators, but time-interleaved (TI) ΣΔ modulators are sensitive to channel mismatch, which causes the quantization noise folded back into the band of interest. To reduce the folded noise caused by the channel mismatch of two-channel TI ΣΔ modulators, a low-power second-order two-channel TI ΣΔ modulator is proposed. The noise transfer function (NTF) of the modulator is a band-pass filter. By using this band-pass NTF, the folded noised can be reduced. The entire modulator can be implemented by employing three op-amps, which is beneficial for power consumption. The circuit of implementation for the proposed modulator is designed in 0.18 µm COMS technology. The proposed modulator can achieve a SNDR of 78.9 dB with a channel mismatch of 0.5% and a linear gradient mismatch of 0.4% for unity sampling capacitors. Monte Carlo simulation is done with a random Gaussian mismatch of 0.4% standard deviation for all capacitors, resulting in an average SNDR of 80.5 dB. It is indicated that the proposed TI modulator is insensitive to the channel mismatch. The total power consumption is 19.5 mW from a 1.8 V supply.

A time-interleaved ADC system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. Mismatches among channel ADCs degrade SNR and SFDR of the ADC system as a whole, and the effects of offset, gain and bandwidth mismatches as well as timing skew of the clocks distributed to the channels have been well investigated. This paper investigates the channel linearity mismatch effects in the time-interleaved ADC system, which are very important in practice but had not been investigated previously. We consider two cases: differential nonlinearity mismatch and integral nonlinearity mismatch cases. Our numerical simulation shows distinct features of such mismatch especially in frequency domain. The derived results can be useful for deriving calibration algorithms to compensate for the channel mismatch effects.