Time stamping is a technique used to prove the existence of certain digital data prior to a specific point in time. With the recent expansion of electronic commerce, it has been widely recognized as an important technique for ensuring the integrity of digital data for a long time period. Recently, various time stamping schemes have been proposed. However, a framework for evaluating their security and cost has not yet been established. Therefore, it has been difficult for users and system designers to select appropriate time stamping schemes. This paper presents a new framework for evaluating the security and cost of time stamping schemes. Our framework classifies time stamping schemes into 108 categories and clarifies their characteristics with regard to security and cost. By applying our framework to a certain scheme, we can easily evaluate its security and cost without discussing details of its specification. In this paper, we explain the basic idea of our framework and show how to use it by applying it to four existing schemes: Digital Notary/SecureSeal, PKITS, TIMESEC and Cuculus.

This paper describes an application of a speech translation system to another task/domain in the real-world by using developmental data collected from real-world interactions. The total cost for this task-alteration was calculated to be 9 Person-Month. The newly applied system was also evaluated by using speech data collected from real-world interactions. For real-world speech having a machine-friendly speaking style, the newly applied system could recognize typical sentences with a word accuracy of 90% or better. We also found that, concerning the overall speech translation performance, the system could translate about 80% of the input Japanese speech into acceptable English sentences.

Following a discussion of various testing methods used in the electron beam (EB) test system, new waveform-based and image-based approaches in the CAD-linked electron beam (EB) test system are proposed. A waveform-based automatic tracing algorithm of the transistor-level performance faults is first discussed. Then, the method to improve the efficiency of an image-based method called dynamic fault imaging (DFI) by fully utilizing the CAD data is described. Third, the VLSI development cost is analyzed by using the fault models that make possible to take into consideration the effect of new testing technologies such as EB testing and focused ion beam (FIB) microfabrication. Finally, the future prospects are discussed.

The Asynchronous Transfer Mode (ATM) is expected to be the basic transmission technology for B-ISDN. Before this happens, however, it will be necessary to predict the impact of fully-deployed ATM-based networks quantitatively. This paper compares the cost-efficiency of an ATM-based network with that of an STM-based network and clarifies the applicable areas of ATM network configurations, in terms of required facilities and considering the effect of statistical multiplexing. It shows cost-effective network configurations based on different service classes and a network configuration suited to ATM. It also discusses the effect of a Synchronous Digital Hierarchy architecture for Virtual Path dimensioning.