We propose and demonstrate a new fabrication process of a microchannel using the Damascene process. This process aims to integrate photonic circuits with microchannels fabricated in a glass film. The microchannel is fabricated by the removal of the sacrificial layer after a sacrificial layer is formed by the Damascene process and the cover is formed by sputter deposition. A thin cover layer can be formed by the sacrificial method, because the cover layer is supported by the sacrificial layer during film formation. The cover layer is hermetically sealed, since it is formed by radio frequency (RF) sputtering deposition. The thickness is 1 µm and the width ranges from 3.5 to 8 µm. Using the proposed microchannel fabrication method, we prepared a microelectromechanical system (MEMS) optical switch using microfluidics, and we confirmed its functional operation. This optical switch actuates a minute droplet of liquid injected into the microchannel using Maxwell's stresses. Light propagates straight through the waveguide so that the light passes through the microchannel when the droplet is in the microchannel, but the light rays are completely reflected into a crossed waveguide when the droplet is not in the microchannel. Since this fabrication method uses techniques common to those in the formation of copper wiring in an IC chip, it can be used in the microchannel process.

A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.