Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond

Noriaki ODA; Hiroyuki KUNISHIMA; Takashi KYOUNO; Kazuhiro TAKEDA; Tomoaki TANAKA; Toshiyuki TAKEWAKI; Masahiro IKEDA

doi:10.1093/ietele/e89-c.11.1544

Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond

Noriaki ODA, Hiroyuki KUNISHIMA, Takashi KYOUNO, Kazuhiro TAKEDA, Tomoaki TANAKA, Toshiyuki TAKEWAKI, Masahiro IKEDA

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A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1544-1550

Publication Date: 2006/11/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.11.1544

Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)

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Noriaki ODA, Hiroyuki KUNISHIMA, Takashi KYOUNO, Kazuhiro TAKEDA, Tomoaki TANAKA, Toshiyuki TAKEWAKI, Masahiro IKEDA, "Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 11, pp. 1544-1550, November 2006, doi: 10.1093/ietele/e89-c.11.1544.
Abstract: A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1544/_p

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@ARTICLE{e89-c_11_1544,
author={Noriaki ODA, Hiroyuki KUNISHIMA, Takashi KYOUNO, Kazuhiro TAKEDA, Tomoaki TANAKA, Toshiyuki TAKEWAKI, Masahiro IKEDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond},
year={2006},
volume={E89-C},
number={11},
pages={1544-1550},
abstract={A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.},
keywords={},
doi={10.1093/ietele/e89-c.11.1544},
ISSN={1745-1353},
month={November},}

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TY - JOUR
TI - Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond
T2 - IEICE TRANSACTIONS on Electronics
SP - 1544
EP - 1550
AU - Noriaki ODA
AU - Hiroyuki KUNISHIMA
AU - Takashi KYOUNO
AU - Kazuhiro TAKEDA
AU - Tomoaki TANAKA
AU - Toshiyuki TAKEWAKI
AU - Masahiro IKEDA
PY - 2006
DO - 10.1093/ietele/e89-c.11.1544
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.
ER -