A sweep spectrum analyzer has been improved over the years, but the fundamental method has not been changed before the 'Super Sweep' method appeared. The 'Super Sweep' method has been expected to break the limitation of the conventional sweep spectrum analyzer, a limit of the maximum sweep rate which is in inverse proportion to the square of the frequency resolution. The superior performance of the 'Super Sweep' method, however, has not been experimentally proved yet. This paper gives the experimental evaluation on the 'Super Sweep' spectrum analyzer, of which theoretical concepts have already been presented by the authors of this paper. Before giving the experimental results, we give complete analysis for a sweep spectrum analyzer and express the principle of the super-sweep operation with a complete set of equations. We developed an experimental system whose components operated in an optimum condition as the spectrum analyzer. Then we investigated its properties, a peak level reduction and broadening of the frequency resolution of the measured spectrum, by changing the sweep rate. We also confirmed that the experimental system satisfactorily detected the spectrum at least 30 times faster than the conventional method and the sweep rate was in proportion to the bandwidth of the base band signal to be analyzed. We proved that the 'Super Sweep' method broke the restriction of the sweep rate put on a conventional sweep spectrum analyzer.

This paper discusses the implementation of multi-band digital intermediate frequency (IF) for wideband CDMA (W-CDMA) transceiver. The majority of the implemented module in hardware is composed of wideband analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and field programmable-gated-arrays (FPGA). And in software, it is coded by VHSIC hardware description language (VHDL) for realizing digital filters and numerically controlled oscillator, etc. To cope with the hardware limitation such as the number of gates in FPGA, the overall digital filter embedded in transceiver is constructed via a cascading a series of decimation and interpolation filters. At transmitter, in order to upconvert the multi-band baseband channels simultaneously, two-stage digital complex quadrature modulation (DCQM) is utilized. The relevant up-and-down conversion of the numerically controlled oscillator (NCO) is designed in the form of a look-up-table (LUT), having samples associated with a sampled sinusoidal with period of 1/4. At receiver, to avoid the usage of surface acoustic wave (SAW) filter, the high-performance digital filter is implemented subject to satisfying band rejection ratio prescribed in blocker and adjacent channel specification. This paper provides the performance of the implemented digital IF module by revealing the results taken from the measurement instruments. Moreover, to confirm its validity computer simulations are simultaneously conducted.

The software-defined radio technique translates the traditional hardware radio platform to a flexible software radio platform that can support multiple air interface standards. This work proposes an efficient IF processing architecture based on software-defined radio for 2G GSM/IS-95 and 3G W-CDMA systems. Hardware complexity is estimated by fixed-point simulation. IF processing architecture should be highly flexible and minimally complex. Firstly, a carrier channel is selected from a wide frequency band using a high-resolution numerically controlled oscillator (NCO). Wide-range interpolation/decimation is performed by the cascaded integrator comb (CIC) filter that involves no multiplier nor stores filter coefficients. Both the desired narrowband and the desired wideband signals can be extracted. The look-up table (LUT), based on the distributed arithmetic (DA) algorithm is used to implement the finite impulse response (FIR) filter. Therefore, a small area and high speed can be achieved. The errors caused by truncation, quantization, rounding-off and overflow are predicted using a fixed-point simulation. These predictions will help to evaluate the word-length for VLSI implementation. Finally, ALTERA APEX20KE is used as a target device. One hundred thousand gates are used for the implementation. Thus, the proposed architecture has high processing flexibility and small area.