The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] digital still camera(2hit)

1-2hit
  • An Image Stabilization Technology for Digital Still Camera Based on Blind Deconvolution

    Haruo HATANAKA  Shimpei FUKUMOTO  Haruhiko MURATA  Hiroshi KANO  Kunihiro CHIHARA  

     
    PAPER-Image Processing and Video Processing

      Vol:
    E94-D No:5
      Page(s):
    1082-1089

    In this article, we present a new image-stabilization technology for still images based on blind deconvolution and introduce it to a consumer digital still camera. This technology consists of three features: (1)double-exposure-based PSF detection, (2)efficient image deblurring filter, and (3)edge-based ringing reduction. Without deteriorating the deblurring performance, the new technology allows us to reduce processing time and ringing artifacts, both of which are common problems in image deconvolution.

  • VLSI Design for Embedded Digital Watermarking JPEG Encoder Based on Digital Camera System

    Tsung-Han TSAI  Chrong-Yi LU  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E87-A No:7
      Page(s):
    1772-1780

    In this paper a new watermarking technique which is combined with joint photographic experts group (JPEG) encoding system is presented. This method operates in the frequency domain by embedding a pseudo-random sequence of real numbers in a selected set of discrete cosine transform (DCT) coefficients. The embedded sequence is extracted without restoring the original image to fit the trend in the digital still camera (DSC) system. The proposed technique represents a major improvement on methods relying on the comparison between the watermarked and original images. Experimental results show that the proposed watermarking method is robust to several common image processing techniques, including JPEG compression, noise, and blurring. We also implement the whole design by synthesizing with TSMC 1P4M 0.35 µm standard cell. The chip size is 3.0643.064 mm2 for 46374 gate counts. The simulation speed can reach 50 MHz. The power dissipation is 69 mW at 3.3 V 50 MHz.