In this letter, an improved triple-tunable frequency synthesizer structure to achieve both high frequency resolution and fast switching speed without degradation of spurious signals (spurs) level performance is proposed. According to this structure, a high performance millimeter-wave frequency synthesizer with low spurious, low phase noise, and fast switching speed, is developed. This synthesizer driven by the direct digital synthesizer (DDS) AD9956 can adjust the output of a DDS and frequency division ratios of two variable frequency dividers (VFDs) to move the spurious components outside the loop bandwidth of the phase-locked loop (PLL). Moreover, the ADF4252 based microwave PLL can further suppress the phase noise. Experimental results from the implemented synthesizer show that remarkable performance improvements have been achieved.

This paper presents a novel spur suppression technique using a three-phase holding pulse for a direct digital synthesizer (DDS) with a two-phase holding digital-to-analog converter (2PH-DAC). A 2PH-DAC, which uses a reverse-sign step-function as a sampling pulse waveform instead of a commonly-used gate function of zeroth-order hold, enhances the first image of aliasing, which is of higher frequency than the fundamental. Therefore, the first image can be treated as a desired signal, while the fundamental and the second image are spurs for a DDS with a 2PH-DAC (2PH-DDS). The main problem of the 2PH-DDS is close spurs in the case that signal frequency is near Nyquist frequency or sampling frequency. This paper proposes a novel spur suppression technique for a 2PH-DDS. A configuration of a 2PH-DDS is first explained, and spectral properties are analyzed. Based on the analysis, a technique using a three-phase holding pulse to cancel spurs is proposed. Evaluated spur levels of the proposed synthesizer are from -51 to -34 dBc, and are improved by 25 dB or more by the proposed technique.

This paper analyzes the spurious sources in DDS synthesizers and deduces the simple model of DDS output signal. The method of feeding pseudo-random noise into the phase accumulator for spurious reduction is discussed. A new method for spurious reduction by compensating for DAC integer nonlinearity is proposed with two DACs and a power combiner. One DAC generates the error signal to compensate for the other DAC INL. The factor how the amplitude error and the phase error between the two combined signals affect the spurious level is also analyzed. The experiment shows that the spurious reduction can be improved by at least 18 dB, which proves the validity of the DAC INL compensation method for the spurious reduction.

This paper presents novel phase-continuous frequency hopping (FH) control for a direct frequency synthesizer (DFS) using a quadrature mixer driven by two direct digital synthesizers (DDSs). To achieve wideband FH in both of the lower and the upper sidebands of a local frequency in a quadrature mixer, the proposed DFS decreases or increases the phase of DDS output signals corresponding to frequency offset from a local frequency of the quadrature mixer. To realize phase decrement, the proposed method adds a complement number in a phase accumulator of a DDS, while a conventional DDS does not use phase decrement but uses a switchable combiner. In addition, as the phase accumulator output changes continuously by summing phase increment, the proposed method always assures phase continuity of a DFS output signal, which ends up suppressing sidelobe level of frequency hopped signals. The calculation and measurement results indicate that a sidelobe of a signal spectrum using the proposed phase continuous method is approximately 10 dB better than that using a conventional phase discontinuous method.

This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

We have developed a new type of phase interpolation direct digital synthesizer (DDS) with a symmetrically structured delay generator. The new DDS is similar to a sine output DDS in that it produces lower spurious signals, but it does not require a sine look-up table. The symmetrically structured delay generator reduces the periodic jitter in the most significant bit (MSB) of the DDS accumulator. The symmetrical structure enables the delay generator to produce highly accurate delay timing and eliminates the need to adjust the circuit constants. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.

We have developed a new type of phase interpolation DDS with a digitally controlled delay generator. The new DDS is similar to a sine output DDS in that it produces low spurious signals, but it does not require a sine look-up table. Periodic jitter in the MSB of the DDS accumulator is reduced with the digitally controlled delay generator. Experimental results confirm successful frequency synthesizer operation in which the spurious signal level is successfully reduced to less than that the MSB of the accumulator.