We propose an effective dopant pile-up model which is useful for device optimization in a short-term. Our purpose is that the model provides speedy calculation for numerous simulations constructed by design of experiment (DoE), and the calibration is also easy in practical range of process condition. The dopant pile-up in the Si/SiO2 interface is calculated using a non-pair diffusion model that solves one equation for each impurity, considering an essential physics where RSCE is due to the dopant pile-up in the Si/SiO2 interface. A non-pair diffusion for dopants and point defects is adequate for time length which can ignore their reactions. The key for the modeling of RSCE is that the dependence on various processes such as channel implantation and annealing conditions can be reproduced in the local process window. The capability of the model is investigated though the comparison to measurements in actual n-channel MOSFETs for different process technologies. We also check the prediction accuracy of the dopant profiles using our model. As a result, the optimization of 4 parameters for 25 jobs based on DoE is possible less than 2 hours using our model.

This paper describes an effective model which reproduces the dependence on the source/drain (S/D) process of the reverse short channel effect (RSCE) of the MOSFET threshold voltage (Vth). It is useful for local modeling which is effective within the limited process conditions. The proposed model is based on the physics where the key factor of RSCE is the dopant pile-up in the Si/SiO2 interface. The purpose of the model is for TCAD to be put to actual use as a quick solution tool. The calculation cost is much lower than a pair diffusion model, because the model is implemented in a conventional process simulator that solves one equation for each impurity. The capability of the simplified model is investigated for the dependence of various process conditions on the RSCE. Using our model, we also report the application of both the actual n-channel and p-channel MOSFETs.

Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800 or 900. As a result, low sheet resistance of 260 Ω/sq. was obtained for a 24 nm depth junction with antimony. These results indicate that antimony is superior to arsenic as a dopant for ultra shallow extension formation. However, increase in antimony concentration above 11020 cm-3 gives rise to precipitation and it limits the sheet resistance reduction of the antimony doped junctions. Redistribution behaviors of antimony relating to the pileup and the precipitation are discussed utilizing SIMS (Secondary Ion Mass Spectrometry) depth profiles.

We propose an effective model that can reproduce the reverse short channel effect (RSCE) of the threshold voltage (Vth) of MOSFETs using a conventional process simulator that solves one equation for each impurity. The proposed model is developed for local modeling which is effective within the limited process conditions. The proposed model involves the physics in which RSCE is due to the pile up of channel dopant at the Si/SiO2 interface. We also report the application to actual device design using our model. The calculation cost is much lower than for a pair diffusion model, and device design in an acceptable turn around time is possible.