Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800
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Kentaro SHIBAHARA, "Ultra-Shallow Junction Formation with Antimony Implantation" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1091-1097, May 2002, doi: .
Abstract: Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1091/_p
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@ARTICLE{e85-c_5_1091,
author={Kentaro SHIBAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ultra-Shallow Junction Formation with Antimony Implantation},
year={2002},
volume={E85-C},
number={5},
pages={1091-1097},
abstract={Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Ultra-Shallow Junction Formation with Antimony Implantation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1091
EP - 1097
AU - Kentaro SHIBAHARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800
ER -