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[Keyword] frame buffer(4hit)

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  • A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation

    Hiroyuki UZAWA  Kazuhiko TERADA  Koyo NITTA  

     
    PAPER-Fiber-Optic Transmission for Communications

      Pubricized:
    2020/11/11
      Vol:
    E104-B No:5
      Page(s):
    481-489

    The power consumption of optical network units (ONUs) is a major issue in optical access networks. The downstream buffer is one of the largest power consumers among the functional blocks of an ONU. A cyclic sleep scheme for reducing power has been reported, which periodically powers off not only the downstream buffer but also other components, such as optical transceivers, when the idle period is long. However, when the idle period is short, it cannot power off those components even if the input data rate is low. Therefore, as continuous traffic, such as video, increases, the power-reduction effect decreases. To resolve this issue, we propose another sleep scheme in which the downstream buffer can be partially powered off by cooperative operation with an optical line terminal. Simulation and experimental results indicate that the proposed scheme reduces ONU power consumption without causing frame loss even while the ONU continuously receives traffic and the idle period is short.

  • The Object-Space Parallel Processing of the Multipass Rendering Method on the (Mπ)2 with a Distributed-Frame Buffer System

    Hitoshi YAMAUCHI  Takayuki MAEDA  Hiroaki KOBAYASHI  Tadao NAKAMURA  

     
    PAPER-Computer Architecture

      Vol:
    E80-D No:9
      Page(s):
    909-918

    The multipass rendering method based on the global illumination model can generate the most photo-realistic images. However, since the multipass rendering method is very time consuming, it is impractical in the industrial world. This paper discusses a massively parallel processing approach to fast image synthesis by the multipass rendering method. Especially, we focus on the performance evaluation of the view-dependent object-space parallel processing on the (Mπ)2 which has been proposed in our previous paper. We also propose two kinds of distributed frame buffer system named cached frame buffer and multistage-interconnected frame buffer. These frame buffer systems can solve the access conflict problem on the frame buffer. The simulation results show that the (Mπ)2 has a scalable performance. For example, the (Mπ)2 with more than 4000 processing elements can achieve an efficiency of over 50%. We also show that both of the proposed distributed frame buffer systems can relieve the overhead due to frame buffer access in the (Mπ)2 in the case that a large number of high-performance processing elements are adopted in the system.

  • (Mπ)2: A Hierarchical Parallel Processing System for the Multipass Rendering Method

    Hiroaki KOBAYASHI  Hitoshi YAMAUCHI  Yuichiro TOH  Tadao NAKAMURA  

     
    PAPER-Architectures

      Vol:
    E79-D No:8
      Page(s):
    1055-1064

    This paper proposes a hierarchical parallel processing system for the multipass rendering method. The multipass rendering method based on the integration of radiosity and ray-tracing can synthesize photo-realistic images. However, the method is also computationally expensive. To accelerate the multipass rendering method, the system, called (Mπ)2, employs two kinds of parallel processing schemes. As a coarse-grain parallel processing, object-space parallel processing with multiple processing elements based on the object-space subdivision is adapted, and each processing element (PE) is equipped with multiple pipelined units for a fine-grain parallel processing. To balance load among the system, static load balancing at the PE level and dynamic load balancing at the pipelined unit level within the PE are introduced. Especially, we propose a novel static load allocation scheme, skewed-distributed allocation, which can effectively distribute a three-dimensional object space to one- or two-dimensional processor configuration of the (Mπ)2 system. Simulation experiments show that the two-dimensional (Mπ)2 systems with the skewed-distributed allocation outperform the three-dimensional systems with the non-skewed distributed allocation. Since lower dimensional systems can be built at a lower cost than higher dimensional systems, the skewed-distributed allocation will be meritorious. Besides, by the combination of static load balancing by the skewed-distributed allocation and the dynamic load balancing by dynamic ray allocation within each PE, the system performance can be further boosted. We also propose a cached frame buffer system to relieve access collision on a frame buffer.

  • Emerging Memory Solutions for Graphics Applications

    Katsumi SUIZU  Toshiyuki OGAWA  Kazuyasu FUJISHIMA  

     
    INVITED PAPER

      Vol:
    E78-C No:7
      Page(s):
    773-781

    Ever increasing demand for higher bandwidth memories, which is fueled by multimedia and 3D graphics, seems to be somewhat satisfied with various emerging memory solutions. This paper gives a review of these emerging DRAM architectures and a performance comparison based on a condition to let the readers have some perspectives of the future and optimized graphics systems.