Software defined radio (SDR) technology has been widely applied for its powerful universality and flexibility in the past decade. To address the issue of bandpass sampling of multiband signals, a novel and efficient method of finding the minimum valid sampling frequency is proposed. Since there are frequency deviations due to the channel effect and hardware instability in actual systems, we also consider the guard-bands between downconverted signal spectra in determining the minimum sampling frequency. In addition, the case that the spectra within the sampled bandwidth are located in inverse placement can be avoided by our proposed method, which will reduce the complexity of the succeeding digital signal process significantly. Simulation results illustrate that the proper minimum sampling frequency can be determined rapidly and accurately.

New Recommendation and Future Standards highlight the Power Factor Correction (PFC) converter as a basic requirement for switching power supplies. Most high-frequency power factor correctors use resistor emulation to achieve a near-unity power factor and a small line current distortion. This technique requires forcing the input current with an average-current-mode control to follow the input voltage. Stability of this system was discussed previously by using some linear models. However, in this paper, two nonlinear phenomena have been encountered in the PFC circuit, period doubling bifurcation and chaos. Detection of these new instability phenomena in the stable regions predicted by the prior linear PFC models makes us more susceptible towards them, and reveals the need to consider a nonlinear models. A nonlinear model performing the practical operation of a boost PFC converter has been developed. Then, a simplified and accurate nonlinear model has been proposed and verified experimentally. As a result from this model, instability maps have been introduced to determine the boundary between stable and unstable operating ranges. Then, the period doubling bifurcation has been studied through a new proposed technique based on the capacitor storage energy. It is cleared that, As the load lessens, a required extra storage power is needed to achieve the significant increase in the output voltage. Then, if the PFC system can provide this extra energy, the operation can reach stability with new zero-storage energy else the system will have double-line zero energy that is period doubling bifurcation.

A stability of the cascade two-stage Power-Factor-Correction converter is investigated. The first stage is boost PFC converter to achieve a near unity power factor and the second stage is forward converter to regulate the output voltage. Previous researches studied the system using linear analysis. However, PFC boost converter is a nonlinear circuit due to the existence of the multiplier and the large variation of the duty cycle. Moreover, the effect of the second stage DC/DC converter on the first stage PFC converter adds more complexity to the nonlinear circuit. In this issue, low-frequency instability has been detected in the two-stage PFC converter assuring the limitation of the prior linear models. Therefore, nonlinear model is proposed to detected and explain these instabilities. The borderlines between stable and unstable operation has been made clear. It is cleared that feedback gains of the first stage PFC and the second stage DC/DC converters are the main affected parts to the total system stability. Then, a simplified nonlinear model is provided. Experiment confirm the two models with a good agreement. These nonlinear models have introduced new PFC design scheme by choosing the minimum required output capacitor and the feedback loop design.

From the bifurcation viewpoint, this study examines a boost PFC converter with average-current-mode control. The boost PFC converter is considered to be a nonlinear circuit because of its use of a multiplier and its large duty cycle variation for input current control. However, most previous studies have implemented linear analysis, which ignores the effects of nonlinearity. Therefore, those studies were unable to detect instability phenomena. Nonlinearity produces bifurcations and chaos when circuit parameters change. The classical PFC design is based on a stable periodic orbit that has desired characteristics. This paper describes the main bifurcations that this orbit may undergo when the parameters of the circuit change. In addition, the instability regions in the PFC converter are delimited. That fact is of practical interest for the design process. Moreover, a prototype PFC circuit is introduced to examine these instability phenomena experimentally. Then, a special numerical program is developed. Bifurcation maps are provided based on this numerical study. They give a comprehensive outstanding for stability conditions and identify stable regions in the parameter space. Moreover, these maps indicate PFC converter dynamics, power factors, and regulation. Finally, numerical analyses and experimentation show good agreement.

To sample a band-limited analog signal directly from the high frequency down to the baseband for the digital signal processing with significantly reduced computation, several concepts of the bandpass sampling are introduced. In this paper, a robust bandpass sampling scheme when there exist frequency deviations due to the channel effect and hardware instability is proposed for practical use, and the effects of the frequency deviations are discussed to select a proper sampling frequency.