This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

This paper describes the dependence of the delay time of a CMOS/SIMOX inverter on the gate-overlap capacitance. An analytical delay-time equation for the CMOS/SIMOX inverter, which includes the gate-overlap capacitance, is derived. This equation shows that the feed-forward effect dominates the characteristics of inverters with a small fanout. The validity of the delay-time equation is confirmed by the comparison to experimental measurements of 0.4-µm CMOS/SIMOX devices. Moreover, a sensitivity analysis shows that it is very important to reduce the gate-drain overlap capacitance for fabricating high-speed scaled-down CMOS/SIMOX devices.