Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance

Takakuni DOUSEKI; Kazuo AOYAMA; Yasuhisa OMURA

Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance

Takakuni DOUSEKI, Kazuo AOYAMA, Yasuhisa OMURA

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This paper describes the dependence of the delay time of a CMOS/SIMOX inverter on the gate-overlap capacitance. An analytical delay-time equation for the CMOS/SIMOX inverter, which includes the gate-overlap capacitance, is derived. This equation shows that the feed-forward effect dominates the characteristics of inverters with a small fanout. The validity of the delay-time equation is confirmed by the comparison to experimental measurements of 0.4-µm CMOS/SIMOX devices. Moreover, a sensitivity analysis shows that it is very important to reduce the gate-drain overlap capacitance for fabricating high-speed scaled-down CMOS/SIMOX devices.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.8 pp.1325-1332

Publication Date: 1993/08/25

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Type of Manuscript: PAPER

Category: Electronic Circuits

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Takakuni DOUSEKI, Kazuo AOYAMA, Yasuhisa OMURA, "Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 8, pp. 1325-1332, August 1993, doi: .
Abstract: This paper describes the dependence of the delay time of a CMOS/SIMOX inverter on the gate-overlap capacitance. An analytical delay-time equation for the CMOS/SIMOX inverter, which includes the gate-overlap capacitance, is derived. This equation shows that the feed-forward effect dominates the characteristics of inverters with a small fanout. The validity of the delay-time equation is confirmed by the comparison to experimental measurements of 0.4-µm CMOS/SIMOX devices. Moreover, a sensitivity analysis shows that it is very important to reduce the gate-drain overlap capacitance for fabricating high-speed scaled-down CMOS/SIMOX devices.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_8_1325/_p

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@ARTICLE{e76-c_8_1325,
author={Takakuni DOUSEKI, Kazuo AOYAMA, Yasuhisa OMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance},
year={1993},
volume={E76-C},
number={8},
pages={1325-1332},
abstract={This paper describes the dependence of the delay time of a CMOS/SIMOX inverter on the gate-overlap capacitance. An analytical delay-time equation for the CMOS/SIMOX inverter, which includes the gate-overlap capacitance, is derived. This equation shows that the feed-forward effect dominates the characteristics of inverters with a small fanout. The validity of the delay-time equation is confirmed by the comparison to experimental measurements of 0.4-µm CMOS/SIMOX devices. Moreover, a sensitivity analysis shows that it is very important to reduce the gate-drain overlap capacitance for fabricating high-speed scaled-down CMOS/SIMOX devices.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance
T2 - IEICE TRANSACTIONS on Electronics
SP - 1325
EP - 1332
AU - Takakuni DOUSEKI
AU - Kazuo AOYAMA
AU - Yasuhisa OMURA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1993
AB - This paper describes the dependence of the delay time of a CMOS/SIMOX inverter on the gate-overlap capacitance. An analytical delay-time equation for the CMOS/SIMOX inverter, which includes the gate-overlap capacitance, is derived. This equation shows that the feed-forward effect dominates the characteristics of inverters with a small fanout. The validity of the delay-time equation is confirmed by the comparison to experimental measurements of 0.4-µm CMOS/SIMOX devices. Moreover, a sensitivity analysis shows that it is very important to reduce the gate-drain overlap capacitance for fabricating high-speed scaled-down CMOS/SIMOX devices.
ER -