The load-independent zero-voltage switching class-E inverter has garnered considerable interest as an essential component in wireless power transfer systems. This inverter achieves high efficiency across a broad spectrum of load conditions by incorporating a load adjustment circuit (LAC) subsequent to the resonant filter. Nevertheless, the presence of the LAC influences the output impedance of the inverter, thereby inducing a divergence between the targeted and observed output power, even in ideal lossless simulations. Consequently, iterative adjustments to component values are required via an LC element implementation. We introduce a novel design methodology that incorporates an external quality factor on the side of the resonant filter, inclusive of the LAC. Thus, the optimized circuit achieves the intended output power without necessitating alterations in component values.

This paper proposes an analytical model of maximum operating frequency of class-D zero-voltage-switching (ZVS) inverter. The model includes linearized drain-source parasitic capacitance and any duty ratio. The nonlinear drain-source parasitic capacitance is equally linearized through a charge-related equation. The model expresses the relationship among frequency, shunt capacitance, duty ratio, load impedance, output current phase, and DC input voltage under the ZVS condition. The analytical result shows that the maximum operating frequency under the ZVS condition can be obtained when the duty ratio, the output current phase, and the DC input voltage are set to optimal values. A 650 V/30 A SiC-MOSFET is utilized for both simulated and experimental verification, resulting in good consistency.

The misalignment of a coupler is a significant issue for capacitive wireless power transfer (WPT). This paper presents a capacitive WPT system specifically designed for underwater drones operating in flowing freshwater environments. The primary design features include a capacitive coupler with an opposite relative position between feeding and receiving points on the coupler electrode, two phase compensation circuits, and a load-independent inverter. A stable and energy-efficient power transmission is achieved by maintaining a 90° phase difference on the coupler electrode in dielectrics with a large unloaded quality factor (Q factor), such as in freshwater. Although a 622-mm coupler electrode is required at 13.56MHz, the phase compensation circuits can reduce to 250mm as one example, which is mountable to small underwater drones. Furthermore, the electricity waste is automatically reduced using the constant-current (CC) output inverter in the event of misalignment where efficiency drops occur. Finally, their functions are simulated and demonstrated at various receiver positions and transfer distances in tap water.

Majority operation has been paid attention as a basic element of beyond-Moore devices on which logic functions are constructed from Majority elements and inverters. Several optimization methods are developed to reduce the number of elements on Majority-Inverter Graphs (MIGs) but more area and power reduction are required. The paper proposes a new exact synthesis method for MIG based on a new topological constraint using node levels. Possible graph structures are clustered by the levels of input nodes, and all possible structures can be enumerated efficiently in the exact synthesis compared with previous methods. Experimental results show that our method decreases the runtime up to 25.33% compared with the fence-based method, and up to 6.95% with the partial-DAG-based method. Furthermore, our implementation can achieve better performance in size optimization for benchmark suites.

This paper proposes a topology of high power, MHz-frequency, half-bridge resonant inverter ideal for low-loss Gallium Nitride high electron mobility transistor (GaN-HEMT). General GaN-HEMTs have drawback of low drain-source breakdown voltage. This property has prevented conventional high-frequency series resonant inverters from delivering high power to high resistance loads such as 50Ω, which is typically used in radio frequency (RF) systems. High resistance load causes hard-switching also and reduction of power efficiency. The proposed topology overcomes these difficulties by utilizing a proposed ‘L-S network’. This network is effective combination of a simple impedance converter and a series resonator. The proposed topology provides not only high power for high resistance load but also arbitrary design of output wattage depending on impedance conversion design. In addition, the current through the series resonator is low in the L-S network. Hence, this series resonator can be designed specifically for harmonic suppression with relatively high quality-factor and zero reactance. Low-distortion sinusoidal 3kW output is verified in the proposed inverter at 13.56MHz by computer simulations. Further, 99.4% high efficiency is achieved in the power circuit in 471W experimental prototype.

This paper proposes constant voltage design based on K-inverter for cooperative inductive power transfer (IPT) where a nearby receiver picks up power and simultaneously cooperates in relaying the signal toward another distant receiver. In a cooperative IPT system, wireless power is fundamentally transferred to the nearby receiver via one K-inverter and to the distant receiver via two K-inverters. By adding one more K-inverter to the nearby receiver, our design is among the simplest methods as it delivers constant output voltage to each receiver via two K-inverters only. Experimental results verify that the proposed cooperative IPT system can stabilize two output voltages against the load variations while attaining high RF-RF efficiency of 90%.

This paper presents a design method of a two-hop wireless power transfer (WPT) system for installing on a robot arm. The class-E inverter and the class-D rectifier are used on the transmission and receiving sides, respectively, in the proposed WPT system. Analytical equations for the proposed WPT system are derived as functions of the geometrical and physical parameters of the coils, such as the outer diameter and height of the coils, winding-wire diameter, and number of turns. Using the analytical equations, we can optimize the WPT system to obtain the design values with the theoretically highest power-delivery efficiency under the size limitation of the robot arm. The circuit experiments are in quantitative agreement with the theoretical predictions obtained from the analysis, indicating the validity of the analysis and design method. The experimental prototype achieved 83.6% power-delivery efficiency at 6.78MHz operating frequency and 39.3W output power.

The hybrid precoding (HP) technique has been widely considered as a promising approach for millimeter wave communication systems. In general, the existing HP structure with a complicated high-resolution phase shifter network can achieve near-optimal spectral efficiency, however, it involves high energy consumption. The HP architecture with an energy-efficient switch network can significantly reduce the energy consumption. To achieve maximum energy efficiency, this paper focuses on the HP architecture with switch network and considers a novel adaptive analog network HP structure for such mmWave MIMO systems, which can provide potential array gains. Moreover, a multiuser adaptive coordinate update algorithm is proposed for the HP design problem of this new structure. Simulation results verify that our proposed design can achieve better energy efficiency than other recently proposed HP schemes when the number of users is small.

A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.

This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-µm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181fJ/Conv.-step at a 25kS/s sampling rate when the supply voltage VDD is 1.2V.

Design of lumped-element immittance inverters which support dual-frequency operation and tuning of both operational frequencies is presented. Unique properties of the dual-composite right/left-handed transmission lines (D-CRLH TL) give an opportunity to design immittance inverters with two non-multiple operational frequencies and a stop band between them. Replacement of capacitors of D-CRLH TL unit cells with variable ones enables inverter tunability. Tunability analysis of such immittance inverters is given. It is shown that a tuning range of the operational frequencies is limited by a tolerable variation of the inverter parameter. The design concept is verified by results of electromagnetic simulation and measured frequency characteristics of fixed (non-tunable) as well as tunable dual-frequency immittance inverters and dual-band filters using the inverters.

We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

A low loss intelligent power module (IPM) that specifically designed for high performance frequency-alterable air conditioner applications is proposed. This IPM utilizes 600 V trench gate field stop insulated gate bipolar transistors (TFS-IGBTs) as the main switching devices to deliver extremely low conduction and switching losses. In addition, 600 V SiC schottky barrier diodes (SBDs) are employed as the freewheeling diodes. Compared to conventional silicon fast recovery diodes (FRDs) SiC SBDs exhibit practically no reverse recovery loss, hence can further reduce the power loss of the IPM. Experimental results reveal that the power loss of the proposed IPM is between 3.5∼21.7 W at different compressor frequencies from 10 to 70 Hz, which achieving up to 12.5%∼25.5% improvement when compared to the state-of-the-art conventional Si-based IGBT IPM.

We have demonstrated tunable extit{n}-channel fullerene and extit{p}-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO$_{2}$. For both OFET types, the $V_{mathrm{th}}$ can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO$_{2}$. The stability of the shifted $V_{mathrm{th}}$ was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 10$^{6}$ s. For organic CMOS inverter, after applying the program gate voltages for extit{n}-channel fullerene or extit{p}-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60,V for extit{p}-channel OFET, the circuit switched at 4, 8,V, that is close to half supply voltage $V_{mathrm{DD}}$, leading to the maximum electrical noise immunity of the inverter circuit.

This paper studies the simple dynamic binary neural network characterized by the signum activation function, ternary weighting parameters and integer threshold parameters. The network can be regarded as a digital version of the recurrent neural network and can output a variety of binary periodic orbits. The network dynamics can be simplified into a return map, from a set of lattice points, to itself. In order to store a desired periodic orbit, we present two learning algorithms based on the correlation learning and the genetic algorithm. The algorithms are applied to three examples: a periodic orbit corresponding to the switching signal of the dc-ac inverter and artificial periodic orbit. Using the return map, we have investigated the storage of the periodic orbits and stability of the stored periodic orbits.

In this paper, a sepic-type single-stage electronic ballast (STSSEB) is proposed, which is derived from the combination of a sepic converter and a half-bridge inverter. The ballast can not only step down input voltage directly but achieve high power factor, reduce voltage stress, improve efficiency and lower cost. Since component stress is reduced significantly, the presented ballast can be applied to high voltage mains. Derivation of the STSSEB is first presented. Then, analysis, design and practical consideration for the STSSEB are discussed. A 347 Vac 60 W prototype has been simulated and implemented. Simulations and experimental results have verified the feasibility of the proposed STSSEB.

We fabricated solution-processed organic complementary inverters based on α,ω-bis(2-hexyldecyl)sexithiophene (BHD6T) for p-channel and C60-fused N-methylpyrrolidine-meta-dodecyl phenyl (C60MC12) for n-channel. The BHD6T and C60MC12 thin-film transistors showed high field-effect mobilities of 0.035 and 0.057 cm2/Vs, respectively. The complementary inverter with a supply voltage of 50 V exhibited inverting voltages of 26.8 V for forward and 27.0 V for backward sweeps and a high gain of 76.

As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristics of the High-k/Metal Gate MOSFET fabricated with 65 nm CMOS process on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (Vth-inv) of CMOS inverter is reported in this paper.

We have demonstrated the inverter operation of stacked-structure CMOS devices using pentacene and ZnO as active layers. The fabrication process of the device is as follows: A top-gate-type ZnO thin-film transistor (TFT), working as an n-channel transistor, was formed on a glass substrate. Then, a bottom-gate-type pentacene TFT, as a p-channel transistor, was fabricated on top of the ZnO TFT while sharing a common gate electrode. For both TFTs, solution-processed silicone-resin layers were used as gate dielectrics. The stacked-structure CMOS has several advantages, for example, easy patterning of active material, compact device area per stage and short interconnection length, as compared with the planar configuration in a conventional CMOS circuit.

This letter studies application of the growing PSO to the design of DC-AC inverters. In this application, each particle corresponds to a set of circuit parameters and moves to solve a multi-objective problem of the total harmonic distortion and desired average power. The problem is described by the hybrid fitness consisting of analog objective function, criterion and digital logic. The PSO has growing structure and dynamic acceleration parameters. Performing basic numerical experiments, we have confirmed the algorithm efficiency.