IEICE TRANSACTIONS on Electronics
Improvement of Single-Electron Digital Logic Gates by Utilizing Input Discretizers
Summary :
We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.2 pp.285-292
- Publication Date
- 2016/02/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.285
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Tran THI THU HUONG
The University of Electro-Communications,Japan Science and Technology Agency
Hiroshi SHIMADA
The University of Electro-Communications,Japan Science and Technology Agency
Yoshinao MIZUGAKI
The University of Electro-Communications,Japan Science and Technology Agency
Keyword
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Tran THI THU HUONG, Hiroshi SHIMADA, Yoshinao MIZUGAKI, "Improvement of Single-Electron Digital Logic Gates by Utilizing Input Discretizers" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 2, pp. 285-292, February 2016, doi: 10.1587/transele.E99.C.285.
Abstract: We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.285/_p
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@ARTICLE{e99-c_2_285,
author={Tran THI THU HUONG, Hiroshi SHIMADA, Yoshinao MIZUGAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Improvement of Single-Electron Digital Logic Gates by Utilizing Input Discretizers},
year={2016},
volume={E99-C},
number={2},
pages={285-292},
abstract={We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.},
keywords={},
doi={10.1587/transele.E99.C.285},
ISSN={1745-1353},
month={February},}
Copy
TY - JOUR
TI - Improvement of Single-Electron Digital Logic Gates by Utilizing Input Discretizers
T2 - IEICE TRANSACTIONS on Electronics
SP - 285
EP - 292
AU - Tran THI THU HUONG
AU - Hiroshi SHIMADA
AU - Yoshinao MIZUGAKI
PY - 2016
DO - 10.1587/transele.E99.C.285
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2016
AB - We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.
ER -
English
