We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

We present calculations of the linear-response conductance of a SiGe based single-electron transistor (SET). The conductance and the discrete charging of the quantum dot are calculated by free-energy minimization. The free-energy calculation takes the discrete level-spectrum as well as complex many-body interactions into account. The tunneling rates for tunneling through the source and lead barrier are calculated using Bardeen's transfer Hamiltonian formalism. The tunneling matrix elements are calculated for transitions between the zero-dimensional states in the quantum dot and the lowest subband in the one-dimensional constriction. We compare the results for the conductance peaks with those from calculations with a constant tunneling rate where the shape of the peaks is only due to energetic arguments.

A simple circuit structure implementing digital-to-analog data conversion function is presented. The proposed digital-to-analog converter utilizes the inherent characters of single-electron tunneling which consist of the periodic voltage oscillation and the ability of counting the number of trapped charges. It produces an analog output voltage for a given digital input. We proposed the device structure performing the weighted summation of inputs, which is converted into an analog voltage by the proposed sensing circuit. Monte Carlo simulation results give us the clear performance of the 3-bit digital-to-analog conversion function and the effect of temperature, capacitance variations, and background charge fluctuations. Moreover, we examined the possibility of extending a N-bit digital-to-analog converter with the proposed scheme.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.