Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.

We review recent progress in integrated photonics devices and their applications for datacom. In addition to current technology used in 100-Gigabit Ethernet (100GbE) with a compact form-factor of the transceiver, the next generation of technology for 400GbE seeks a larger number of wavelengths with a more sophisticated modulation format and higher bit rate per wavelength. For wavelength scalability and functionality, planar lightwave circuits (PLCs), such as arrayed waveguide gratings (AWGs), will be important, as well higher-order-modulation to ramp up the total bit rate per wavelength. We introduce integration technology for a 100GbE optical sub-assembly that has a 4λ x 25-Gb/s non-return-to-zero (NRZ) modulation format. For beyond 100GbE, we also discuss applications of 100GbE sub-assemblies that provide 400-Gb/s throughput with 16λ x 25-Gb/s NRZ and bidirectional 8λ x 50-Gb/s four-level pulse amplitude modulation (PAM4) using PLC cyclic AWGs.

On-chip neural interface devices based on CMOS image sensor technology are proposed and demonstrated. The devices were designed with target applications to optogenetics in bioscience. Multifunctional CMOS image sensors equipped with an addressable on-chip electrode array were integrated with a functional interface chip that contained embedded GaInN light emitting diodes (LEDs) and electrodes to create a neural interface. Detailed design information regarding the CMOS sensor chip and the functional interface chip including the packaging structure and fabrication processes are presented in this paper. The on-chip optical stimulation functionality was demonstrated in an in vitro experiment using neuron-like cells cultured on the proposed device.

This paper describes recent progress of photonically-enabled systems for millimeter-wave and terahertz measurement applications. After briefly explaining signal generation schemes as a foundation of photonics-based approach, system configurations for specific applications are discussed. Then, practical demonstrations are presented, which include frequency-domain spectroscopy, phase-sensitive measurement, electric-field measurement, and 2D/3D imaging.

High structural perfection, wafer uniformity, and reproducibility are key parameters for high-volume, low cost manufacture of resonant tunnelling diode (RTD) terahertz (THz) devices. Low-cost, rapid, and non-destructive techniques are required for the development of such devices. In this paper, we report photoluminescence (PL) spectroscopy as a non-destructive characterisation technique for high current densityInGaAs/AlAs/InP RTD structures grown by metal-organic vapour phase epitaxy (MOVPE) for THz applications. By using a PL line scanning technique across the edge of the sample, we identify characteristic luminescence from the quantum well (QW) and the undoped/n⁺ InGaAs layers. By using the Moss-Burstein effect, we are able to measure the free-electron concentration of the emitter/collector and contact layers in the RTD structure. Whilst the n⁺ InGaAs luminescence provides information on the doping concentration, information on the alloy composition and compositional variation is extracted from the InGaAs buffer layer. The QW luminescence provides information on the average well width and provides a monitor of the structural perfection with regard to interface and alloy disorder.

The traffic of the future aggregation network will dynamically change not only in volume but also destination to support the application of virtualization technology to network edge equipment to achieve cost-effectiveness. Therefore, future aggregation network will have to accommodate this traffic cost-effectively, despite dynamic changes in both volume and destination. To correspond to this trend, in this paper, we propose an optical layer 2 switch network based on bufferless optical time division multiplexing (TDM) and dynamic bandwidth allocation to achieve a future aggregation network cost-effectively. We show here that our proposed network architecture effectively reduced the number of wavelengths and optical interfaces by application of bufferless optical TDM technology and dynamic bandwidth allocation to the aggregation network.

Flexible resource utilization in terms of adaptive use of optical bandwidth with agile reconfigurability is key for future metro networks. To address this issue, we focus on optical subwavelength switched network architectures that leverage high-speed optical switching technologies and can accommodate dynamic traffic cost-effectively. Although optical subwavelength switched networks have been attracting attention, most conventional studies apply static (pre-planned) protection scenarios in the networks of limited sizes. In this paper, we discuss optical switch requirements, the use of transceivers, and protection schemes to cost-effectively create large-scale reliable metro networks. We also propose a cost-effective adaptive protection scheme appropriate for optical subwavelength switched networks using our fast time-slot allocation algorithm. The proposed scheme periodically re-optimizes the bandwidth of both working and protection paths to prevent bandwidth resources from being wasted. The numerical examples verify the feasibility of our proposed scheme and the impact on network resources.

Recent small cube satellites use higher frequency bands such as Ku-band for higher throughput communications. This requires high-frequency link in an earth radio station as well. As one of the solutions, we propose usage of bidirectional radio-on-fiber link employing a wavelength multiplexing scheme. It was numerically shown that the response linearity of the electro-absorption modulator integrated laser (EML) is sufficient and that the spurious emissions are lower enough or can be reduced by the radio-frequency filters. From the frequency response and the single-sideband phase noise measurements, the EML was proved to be used in a radio-on-fiber system of the cube satellite earth station.

Conversion between multi-level modulation formats is one of key processing functions for flexible networking aimed at high spectral efficiency (SE) in optical fiber transmission. The authors previously proposed an all-optical format conversion system from binary phase-shift keying (BPSK) to quadrature PSK (QPSK) and reported an experimental demonstration. In this paper, we consider its reversed conversion, that is, from QPSK to BPSK. The proposed system consists of a highly nonlinear fiber used to generate complex conjugate signal, and a 3-dB directional coupler used to produce converted signals by interfering the incident signal with the complex conjugate signal. The incident QPSK stream is converted into two BPSK tributaries without any loss of transmitting data. We show the system performances such as bit-error-rate and optical signal-to-noise ratio penalty evaluated by numerical simulation.

We experimentally investigate the performance of a distributed Raman amplifier (DRA)-based pulse compressor for a phase modulated signal. A 10 Gb/s return-to-zero (RZ)-differential phase shift keying (DPSK) signal is compressed to picosecond range after transmission. Pulsewidth is continuously compressed in a wide range from 20 to 3.2 ps by changing the pump power of the DRA while the compressed waveforms are well-matched with sech² function. Error-free operations at bit-error-rate (BER) of 10^-9 are achieved for the compressed signals of various pulsewidths with low power penalties within 2.3 dB compared to the back-to-back. After the compression, the 10 Gb/s signal is used to generate a 40 Gb/s RZ-DPSK optical time division multiplexing (OTDM) signal. This 40 Gb/s OTDM signal is then successfully demultiplexed to 10 Gb/s DPSK signal by using an optical gate based on four-wave mixing (FWM) in a highly nonlinear fiber (HNLF).

A new design method for a high-order series-coupled microring filter using Chebyshev filter condition was proposed and its application to the design of a wavelength-selective switch (WSS) was discussed. In the proposed method, the propagation loss in a microring resonator, coupling loss at a coupler, and a free spectral ranges (FSR) in a microring resonator are considered for the first time. It was found that for high-order series coupled microring resonators, the WSS designed using Chebyshev condition has more boxlike filter responses and high extinction ratio, compared with that designed using Butterworth condition, in the case where the round-trip loss in a microring is relatively large. In addition, the fourth-order series-coupled microring WSS with boxlike responses was successfully designed, considering Vernier effect for a larger FSR and shift in resonant wavelength.

We describe a physical-contact (PC) multicore fiber (MCF) connector with good optical characteristics. To achieve stable physical-contact connection, we clarify the relationship between connector-end deformation and compression force with spherical polished ferrule end structures using finite element analysis and actual measurements. On the basis of the obtained relationship, we demonstrate a design approach that shows the physical-contact condition of all the cores of a multicore fiber with a simplex connector. In addition, we clarify the design criteria for low-loss connection by employing a rotational angle alignment structure, and devise an SC-type rotational MCF connector with high alignment accuracy. Based on our designs for PC and low-loss connection, we demonstrate an MCF connector with PC connection that provides a sufficiently high return loss exceeding 50dB and a sufficiently low connection loss of below 0.2dB for all the cores of a 7-core single-mode MCF.

We have developed a wavelength-swept laser source with ultrahigh phase stability. A potassium tantalate niobate (KTa_1-xNb_xO₃, KTN) single crystal was employed as an electro-optic deflector for a high-speed wavelength sweep in the laser cavity. The device structure and performance of a KTN deflector is described. The device includes the beam-shaping optics, which can enhance the resolution of a KTN deflector. A 200-kHz sweep rate was obtained with an average output power of 20mW and a coherence length of 8mm for a wavelength range exceeding 100nm. We demonstrated a swept source with ultrahigh phase stability in the 1.3µm wavelength range as a result of the low-jitter operation of the deflector. The standard deviation of timing jitters measured between adjacent A-lines was confirmed to be less than 78ps, which corresponds to a phase difference of 0.017 radians at a Michelson interferometer path difference of 1.5mm. In addition to realizing the phase stability of neighboring A-lines, a long-term stable sweep was demonstrated by eliminating the refresh operation that was previously needed to prevent output power decay.

In this study, to obtain a more accurate analysis of the temperature in microwave coagulation therapy (MCT) for liver cancer, the water content ratios of dehydrated liver tissue and the dependencies of the dielectric and thermal constants of the tissue on the water content ratios were investigated in tissue heated at 2.45GHz. Swine liver tissues were heated and dehydrated under various conditions, and the water content ratios and dielectric and thermal constants were measured. The results indicated that the water content ratio of the tissue depended on the heating temperature and that the dielectric constants (relative permittivity and electrical conductivity) and thermal constants (specific heat and thermal conductivity) of the dehydrated tissues strongly depended on the water content ratio. Based on these results, numerical analyses of the electromagnetic field and temperature inside the liver tissue heated with a coaxial-slot antenna were conducted. Incorporating information on the water content ratio improved the accuracy of temperature calculations in MCT.

This paper proposes a novel image integral equation of the first type (IIE-1) for a TE plane wave scattering from periodic rough surfaces with perfect conductivity by means of the method of image Green's function. Since such an IIE-1 is valid for any incident wavenumbers including the critical wavenumbers, the analytical properties of the scattered wavefield can be generally and rigorously discussed. This paper firstly points out that the branch point singularity of the bare propagator inevitably appears on the incident wavenumber characteristics of the scattered wavefield and its related quantities just at the critical wavenumbers. By applying a quadrature method, the IIE-1 becomes a matrix equation to be numerically solved. For a periodic rough surface, several properties of the scattering are shown in figures as functions of the incident wavenumbers. It is then confirmed that the branch point singularity clearly appears in the numerical solution. Moreover, it is shown that the proposed IIE-1 gives a numerical solution satisfying sufficiently the optical theorem even for the critical wavenumbers.

This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.

We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

This paper presents a novel low-power decoder architecture for the (36420, 32778) binary LDPC code targeting energy-efficient NAND-flash-based mobile devices. The proposed energy-scalable decoding algorithm reduces the operating bit-width of decoding function units at the early-use stage where the channel condition is good enough to lower the precision of computation. Based on a flexible adder structure, the decoding energy of the proposed LDPC decoder can be reduced by freezing the unnecessary parts of hardware resources. A prototype 4KB LDPC decoder is designed in a 65nm CMOS technology, which achieves an average decoding throughput of 8.13Gb/s with 1.2M equivalent gates. The power consumption of the decoder ranges from 397mW to 563mW depending on operating conditions.

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si_1-xGe_x virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si_1-xGe_x virtual substrate. The model is found to tally well with the device simulator.

Unlimited requirements for system-on-chip (SoC) facilitate three-dimensional (3D) technology as a promising alternative for extending Moore's Law. In spite of many advantages 3D technology provides, 3D technology faces testing issues because of the complexity of 3D design. Therefore, resolving the problem of test optimization and reducing test cost are crucial challenges. In this paper, we propose a novel optimization mechanism of 3D SoCs to minimize test time for mid-bond testing. To make our proposed mechanism more practical, we discuss test cost in mid-bond testing with consideration of manufacturing influence factors. Experimental results on ITC'02 SoC benchmark circuits show that our proposed mechanism reduces mid-bond test time by around 73% on average compared with one baseline solution, furthermore, the mechanism also proves its capacity in test cost reduction.

Cache memories are the major application of high-speed SRAMs, and they are frequently installed in high performance logic VLSIs including microprocessors. This paper presents a 4-way set-associative, SOI cache-tag memory. To obtain higher operating speed with less power dissipation, we devised an I/O-separated memory cell with a dual-rail wordline, which is used to transmit complementary selection signals. The address decoding delay was shortened using CMOS dual-rail logic. To enhance the maximum operating frequency, bitline's recovery operations after writing data were eliminated using a memory array configuration without half-selected cells. Moreover, conventional, sensitive but slow differential amplifiers were successfully removed from the data I/O circuitry with a hierarchical bitline scheme. As regards the stored data management, we devised a new hardware-oriented LRU-data replacement algorithm on the basis of 6-bit directed graph. With the experimental results obtained with a test chip fabricated with a 0.25-µm CMOS/SIMOX process, the core of the cache-tag memory with a 1024-set configuration can achieve a 1.5-ns address access time under typical conditions of a 2-V power supply and 25^°C. The power dissipation during standby was less than 14 µW, and that at the 500-MHz operation was 13-83 mW, depending on the bit-stream data pattern.