IEICE TRANSACTIONS on Electronics
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface
Summary :
This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.2 pp.275-284
- Publication Date
- 2016/02/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.275
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Toshiyuki KIKKAWA
Graduate School of Engineering, The University of Tokyo
Toru NAKURA
The University of Tokyo
Kunihiro ASADA
Graduate School of Engineering, The University of Tokyo,The University of Tokyo
Keyword
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Toshiyuki KIKKAWA, Toru NAKURA, Kunihiro ASADA, "An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 2, pp. 275-284, February 2016, doi: 10.1587/transele.E99.C.275.
Abstract: This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.275/_p
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@ARTICLE{e99-c_2_275,
author={Toshiyuki KIKKAWA, Toru NAKURA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface},
year={2016},
volume={E99-C},
number={2},
pages={275-284},
abstract={This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.},
keywords={},
doi={10.1587/transele.E99.C.275},
ISSN={1745-1353},
month={February},}
Copy
TY - JOUR
TI - An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface
T2 - IEICE TRANSACTIONS on Electronics
SP - 275
EP - 284
AU - Toshiyuki KIKKAWA
AU - Toru NAKURA
AU - Kunihiro ASADA
PY - 2016
DO - 10.1587/transele.E99.C.275
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2016
AB - This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.
ER -
English
