This paper describes IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, we use five kinds of master-slave D-type flip-flops as the circuit under test. Target faults are two-line resistive bridging faults extracted from a circuit layout. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that IDDQ testing cannot detect faults existing at specific points in some flip-flops, and this problem depends on the flip-flop structure. However, IDDQ testing has high fault coverage ( 98%) compared with traditional logic testing. We also examine performances of fully IDDQ testable flip-flops.

We propose frequency-domain optical code-division-multiplexing (CDM) employing quadrature-amplitude-modulation (QAM) using two of multi-level (M-ary) data generated based on electrical-domain spatial code spreading. Its spectral efficiency is enhanced compared to the conventional scheme with amplitude-shift-keying (ASK) using only one of M-ary data. Although it demands the recovery of amplitude and optical phase information, the practicality of the receiver is retained with self-homodyne detection using a phase-shift-keying (PSK) pilot light. Performance is theoretically evaluated and the optimal parameters are derived. Finally, the feasibility of the proposed technique is experimentally confirmed.

In recent years, the growing density and complexity of VLSIs have led to an increase in the numbers of test patterns and fault models. Test patterns used in VLSI testing are required to provide high quality and low cost. Don't care (X) identification techniques and X-filling techniques are methods to satisfy these requirements. However, conventional X-identification techniques are less effective for application-specific fields such as test compaction because the X-bits concentrate on particular primary inputs and pseudo primary inputs. In this paper, we propose a don't care identification method for test compaction. The experimental results for ITC'99 and ISCAS'89 benchmark circuits show that a given test set can be efficiently compacted by the proposed method.

This paper presents a wide-input-voltage-range and high-efficiency boost converter that is assisted by a transformer-based oscillator. The oscillator can provide a sufficient amount of power to drive a following switched-inductor boost converter at low voltages. Moreover, it adopts a novel amplitude-regulation circuit (ARC) without using high power-consuming protective devices to suppress the expansion of the oscillation amplitude at high input voltages. Therefore, it can avoid over-voltage problems without sacrificing the power efficiency. Additionally, a power-down circuit (PDC) is implemented to turn off the oscillator, when the boost converter can be driven by its own output power, thus, eliminating the power consumption by the oscillator and improving the power efficiency. We implemented the ARC and the PDC with discrete components rather than one-chip integration for the proof of concept. The experimental results showed that the proposed circuit became possible to operate from an input voltage of 60mV to 3V while maintaining high peak efficiency up to 92%. To the best of our knowledge, this converter provides a wider input range in comparison with the previously-published converters. We are convinced that the proposed approach by inserting an appropriate start-up circuit in a commercial converter will be effective for rapid design proposals in order to respond promptly to customer needs as Internet of things (IoT) devices with energy harvester.

High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to decrease the number of transitions on the FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT Solvers that conducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient between transitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.

Silica-LiNbO3 (LN) hybrid modulators have a hybrid configuration of versatile passive silica-based planar lightwave circuits (PLCs) and simple LN phase modulators arrays. By combining the advantages the two components, these hybrid modulators offer large-scale, highly-functionality modulators with low losses for advanced modulation formats. However, the reliability evaluation necessary to implement them in real transmissions has not been reported yet. In terms of reliability characteristics, there are issues originating from the difference in thermal expansion coefficients between silica PLC and LN. To resolve these issues, we propose design guidelines for hybrid modulators to mitigate the degradation induced by the thermal expansion difference. We fabricated several tens of silica-LN dual polarization quadrature phase shift keying (DP-QPSK) modulators based on the design guidelines and evaluated their reliability. The experiment results show that the modules have no degradation after a reliability test based on GR-468, which confirms the validity of the design guidelines for highly reliable silica-LN hybrid modulators. We can apply the guidelines for hybrid modules that realize heterogeneous device integration using materials with different coefficients of thermal expansion.

We developed a high-frequency and integrated design based on a flip-chip interconnection technique (Hi-FIT) as a wire-free interconnection technique that provides a high modulation bandwidth. The Hi-FIT can be applied to various high-speed (>100 Gbaud) optical devices. The Hi-FIT EA-DFB laser module has a 3-dB bandwidth of 59 GHz. And with a 4-intensity-level pulse amplitude modulation (PAM) operation at 107 Gbaud, we obtained a bit-error rate (BER) of less than 3.8×10-3, which is an error-free condition, by using a 7%-overhead (OH) hard-decision forward error correction (HD-FEC) code, even after a 10-km SMF transmission. The 3-dB bandwidth of the Hi-FIT employing an InP-MZM sub-assembly was more than 67 GHz, which was the limit of our measuring instrument. We also demonstrated a 120-Gbaud rate IQ modulation.

We review recent progress in integrated photonics devices and their applications for datacom. In addition to current technology used in 100-Gigabit Ethernet (100GbE) with a compact form-factor of the transceiver, the next generation of technology for 400GbE seeks a larger number of wavelengths with a more sophisticated modulation format and higher bit rate per wavelength. For wavelength scalability and functionality, planar lightwave circuits (PLCs), such as arrayed waveguide gratings (AWGs), will be important, as well higher-order-modulation to ramp up the total bit rate per wavelength. We introduce integration technology for a 100GbE optical sub-assembly that has a 4λ x 25-Gb/s non-return-to-zero (NRZ) modulation format. For beyond 100GbE, we also discuss applications of 100GbE sub-assemblies that provide 400-Gb/s throughput with 16λ x 25-Gb/s NRZ and bidirectional 8λ x 50-Gb/s four-level pulse amplitude modulation (PAM4) using PLC cyclic AWGs.