IEICE TRANSACTIONS on Information
An Analysis of the Relationship between IDDQ Testability and D-Type Flip-Flop Structure
Summary :
This paper describes IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, we use five kinds of master-slave D-type flip-flops as the circuit under test. Target faults are two-line resistive bridging faults extracted from a circuit layout. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that IDDQ testing cannot detect faults existing at specific points in some flip-flops, and this problem depends on the flip-flop structure. However, IDDQ testing has high fault coverage (
- Publication
- IEICE TRANSACTIONS on Information Vol.E81-D No.10 pp.1072-1078
- Publication Date
- 1998/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Fault Tolerant Computing
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Yukiya MIURA, Hiroshi YAMAZAKI, "An Analysis of the Relationship between IDDQ Testability and D-Type Flip-Flop Structure" in IEICE TRANSACTIONS on Information,
vol. E81-D, no. 10, pp. 1072-1078, October 1998, doi: .
Abstract: This paper describes IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, we use five kinds of master-slave D-type flip-flops as the circuit under test. Target faults are two-line resistive bridging faults extracted from a circuit layout. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that IDDQ testing cannot detect faults existing at specific points in some flip-flops, and this problem depends on the flip-flop structure. However, IDDQ testing has high fault coverage (
URL: https://global.ieice.org/en_transactions/information/10.1587/e81-d_10_1072/_p
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@ARTICLE{e81-d_10_1072,
author={Yukiya MIURA, Hiroshi YAMAZAKI, },
journal={IEICE TRANSACTIONS on Information},
title={An Analysis of the Relationship between IDDQ Testability and D-Type Flip-Flop Structure},
year={1998},
volume={E81-D},
number={10},
pages={1072-1078},
abstract={This paper describes IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, we use five kinds of master-slave D-type flip-flops as the circuit under test. Target faults are two-line resistive bridging faults extracted from a circuit layout. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that IDDQ testing cannot detect faults existing at specific points in some flip-flops, and this problem depends on the flip-flop structure. However, IDDQ testing has high fault coverage (
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - An Analysis of the Relationship between IDDQ Testability and D-Type Flip-Flop Structure
T2 - IEICE TRANSACTIONS on Information
SP - 1072
EP - 1078
AU - Yukiya MIURA
AU - Hiroshi YAMAZAKI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E81-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1998
AB - This paper describes IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, we use five kinds of master-slave D-type flip-flops as the circuit under test. Target faults are two-line resistive bridging faults extracted from a circuit layout. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that IDDQ testing cannot detect faults existing at specific points in some flip-flops, and this problem depends on the flip-flop structure. However, IDDQ testing has high fault coverage (
ER -
English
