In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

In a switched-capacitor (SC) circuit, the major block is an operational transconductance amplifier (OTA) designed in order to form a feedback loop. However, the OTA is the block that consumes most of the power in SC circuits. This paper proposes the use of a class-C inverter instead of the OTA in SC circuits and a corresponding switches configuration for extremely low power applications. A detailed analysis and design trade-offs are also provided. Simulation and experimental results show that sufficient performance can be obtained even though a class-C inverter is used. The second-order biquad filter and the second-order SC sigma-delta (ΣΔ) modulator based on a class-C inverter are designed. These circuits have been fabricated with a 0.35-µm CMOS process. The measurement results of the fabricated SC biquad filter show a 59-dB signal-to-noise-plus-distortion ratio (SNDR) for a 0.2-Vp-p input signal and 0.9-V dynamic ranges. The power consumption of the biquad filter is only 0.4 µW with a 1-V power supply. The measurement results of the fabricated ΣΔ modulator show a 61-dB peak SNR for a 1.6-kHz bandwidth with a sample rate of 200 kHz. The modulator consumes 0.8 µW with a 1-V power supply.

This paper deals with a simple and practical power loss analysis simulator, which can actually estimate the total power losses of three phase voltage-fed Auxiliary resonant commutation pole snubber assisted soft switching inverter as well as hard-switching inverter. In order to estimate the switching power losses and conduction power losses of switching semiconductor power devices (IGBTs), which are incorporated into the inverters, the proposed practical simulator is making use of feasible switching power loss data tables and conduction power loss data tables, which are accumulated from the measured voltage and current operating waveforms of power semiconductor switching devices. The practical effectiveness of feasible simulation technique and power loss evaluations for power electronic conversion circuits and systems are confirmed by the simulation and experimental results basis under the conditions of soft switching and hard switching sinusoidal PWM schemes.

A new technique to reduce the isolation network's size in a Marchand balun needed for perfect all-port matching and isolation is proposed. The proposed isolation circuit is realized using a coupled-line phase-inverter in place of the bulky 180line section that has been previously proposed. Analysis of the proposed circuit yields the required relationship between coupling coefficient and electrical length of the coupler. Based on the design equations, the circuit is experimentally demonstrated at 1.8 GHz and has shown excellent results. The obtained output return loss and isolation loss are more than 18 dB and 40 dB, respectively. The proposed balun was then applied to the application of a doubled-balanced ring-diode mixer. The designed mixer achieves a low conversion loss of 6 dB at its operating frequency, which is 1.5 dB lower than for a doubled-balanced diode mixer using a conventional impedance-transforming Marchand balun. The RF-IF and LO-IF isolations are well below 25 dB and 18 dB across 1 GHz RF operating bandwidth, respectively.

In transient analyzing of a crosstalk, the crosstalk waveform can be obtained with a commercial simulator such as SPICE simulation or FDTD (Finite Difference Time Domain) simulation. In case of using a simple model, a CMOS-IC load is considered as a constant capacitance load in crosstalk simulation. However, the semiconductor devices, such as CMOS-IC, have a characteristic of nonlinear impedance depending on the input voltage. We measured the far-end crosstalk of two parallel microstrip lines for a CMOS inverter (74HC04) load by changing the magnitude of the input step voltage. As the result, we found that the far-end crosstalk for the CMOS inverter load dose not necessarily depend on the input capacitance of the CMOS inverter.

This paper presents a miniaturized reverse-phase hybrid ring by the use of shunt capacitors, and successfully designs a very miniature hybrid ring of a 0.28-wavelength circumference with a wide bandwidth comparable to the regular reverse-phase hybrid ring based on the equivalent admittance approach. Moreover, a method of broadening the bandwidth with adding a matching network consisting of a very short transmission line and two shunt capacitors at each port is also described. The validity of the proposed design is demonstrated by electromagnetic simulator (Sonnet em) for a uniplanar hybrid ring.

This paper presents an effective approach for estimating of the load matching conditions for dielectric barrier discharge (DBD) load. By the simulation method proposed here, optimal working frequency and optimal applied voltage for driving of DBD load can be calculated. Estimation results for the DBD ultraviolet generation lamp as a load of series resonant inverter are presented here, together with their evaluations.

Low-profile inverter power supplies are increasingly required for backlight systems of liquid crystal displays (LCDs). A great deal of attention has been focused on the application of piezoelectric transformers (PTs) to such power supplies. To miniaturize PT inverters still further, PTs need to have sufficient high voltage-step-up-ratio, which can be achieved by a multilayered PT. First, this paper describes a method for simulating such performance using a distributed constant equivalent circuit model. The results of the simulation for a multilayered PT operated in the third order longitudinal vibration mode show that the resistance of internal electrodes causes the dominant loss factor. Next, a power inverter incorporating the multilayered PT was fabricated. This power inverter can be operated over a wide input DC voltage range from 7-20 V. Regarding a conventional inverter drive circuit, when input DC voltage range was extended, the inverter efficiency remarkably decreased. For the reason, we developed a new inverter circuit, which is equipped with an automatic drive voltage control circuit to maintain the drive voltage to the PT at a constant value. As a result, the fabricated power inverter exhibited more than 90% overall efficiency and 3.5 W output power, which is enough to light up a 12.1-inch color LCD. The maximum luminance efficiency on a light transmission plate of the backlight was as high as 30 cd/m2/W.

This paper describes the circuit design procedure of the zero-current soft switching (ZCS) high frequency inverter for induction heating uses. Its output power can be regulated from its maximum to minimum by the instantaneous current vector control scheme using phase shift control between switching units at a fixed frequency. In addition, it can be safely operated since no extraordinarily high voltage or current results even at a short-circuit period at the load. Also, its overall efficiency reaches 90%. The detailed load and frequency characteristics of the inverter are elucidated by the computer-aided simulation. Then, the circuit design procedure is presented, and practical numerical examples are obtained according to this procedure which reveal that the inverter is highly practical and the design procedure is effective. The trial inverters yielding 2 kW or 4 kW were actually prepared. The observed values of the voltages and currents of the inverters were found to be in good agreement with the calculated ones. These facts certificate the validity of the proposed design procedure.

The analog inverter for realization of the NOT function is the indispensable circuit element in the voltage-mode analog and digital signal processing. In this paper, we propose a novel analog inverter composed of only two neuron-MOS transistors. The analog inverter has the weighted negative feedback mechanism to operate both of neuron-MOS transistors under the saturation region in all input ranges. In verification using HSPICE simulations, the analog inverter performs the high linearity with errors of approximately 40 [mV] in all input ranges, particularly errors of less than 19 [mV] in more than 90% of input ranges. And, the maximum power consumption of the analog inverter is less than 1.5 [µW] although a peak of a standard CMOS inverter is around 30 [µW] under the supply voltage of 3.0 [V]. These good stability and results are produced by the negative feedback. Furthermore, fabrication costs of the analog inverters can be kept at the minimum because neuron-MOS transistors can be actualized in a conventional CMOS process without any additional process. For applications of the analog inverter, the voltage comparator with high noise margins is designed and is applied to the two-input MAX and the two-input MIN circuits in the voltage-mode. The MAX and the MIN circuits for realization of the MAX and the MIN functions, respectively, can be composed of total ten transistors each. They also perform well in verifications. On the basis of the proposed circuits, almost all of voltage-mode multi-valued logic circuits with high-performance can be realized like present binary logic systems. And, the proposed circuits can give full play to the high linearity and advantages for the arbitrary transformation of signal forms in the analog signal processing such as the fuzzy control.

Steady-state characteristics of the push-pull inverter with a piezoelectric transformer are analyzed. The piezoelectric transformer operating in the 3rd-order longitudinal vibration mode is used in place of a conventional magnetic transformer to produce a high output voltage to light up a cold cathode fluorescent lamp. The circuit operation, the load characteristics, the efficiency and the ZVS conditions are analyzed using equivalent circuits. These analytical results are confirmed by experiments. An example of the output current control is also shown.

The dependence of the negative nonlinear absorption effect on the modulation degree and frequency of the incident laser was investigated in Er3+: LiYF4 crystals. With a decreasing modulation degree, a reverse-phased waveform was obtained in the transmitted waveform for modulation intensities of sinusoidal and rectangle waves. The transmitted waveform was observed symmetrically at modulation frequency of 0. 25 MHz. However, the transmitted waveform was asymmetrical at higher than 0. 5 MHz. In addition, the reverse-phased waveforms were obtained for sample lengths greater than 12 mm in the incident modulation degree of 10 to 56%. The NNA effect was observed at a temperature range of 20 to 500 K. It has been confirmed that a mechanism of the negative nonlinear absorption can be explained by considering an enhanced absorption model for a five-level system of the Er3+ ion.

Low-profile, miniaturized and highly efficient power inverters are required to light up backlights, which include cold cathode fluorescent lamps (CCFLs), in color liquid crystal displays (LCDs), replacing conventional power inverters with electromagnetic transformers. The object of this study is to actualize a power inverter to which a novel multilayered piezoelectric ceramic transformer operating in the third order longitudinal mode is applied. The piezoelectric transformer has a symmetrical structure in the lengthwise direction and its generating part operates in a piezoelectric stiffened mode in order to increase both energy conversion efficiency and power density. This transformer has great advantages. Namely, all the electronic terminals in this transformer can be connected at the vibration nodes of the transformer, which contributes to the guarantee of stable transformer performances at high power operation, and this transformer is superior in impedance matching against the backlight load at steady state, because the output impedance of this transformer is much lower than that of conventional Rosen type transformers. Then a power inverter with the transformer was fabricated. In this power inverter, a separately excited oscillation circuit was adopted to drive the transformer with high efficiency, and the transformer drive frequency was controlled by detecting the backlight current in order to adjust the backlight luminance properly. As a result, the fabricated power inverter exhibited more than 90% overall efficiency and 4. 5-W output power, which is enough power to light up a 9. 4 inch color LCD, including the stray capacitance loss resulting from CCFL mounting. The luminance value on a light transmission plate of the backlight was more than 2000 cd/m2.

Analog inverter is one of the most useful building blocks in analog circuits. This paper proposes an analog inverter consisting of a p-channel MOS (PMOS) and an n-channel MOS (NMOS) inverter and presents an application to all-pass filter realizations. The proposed circuit has a wide dynamic range by combining PMOS and NMOS inverters. When the proposed analog inverter is applied to an all-pass filter, the circuit configuration becomes simpler and occupies less chip area and power consumption.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

Threshold voltage shift in high frequency operation of 0.3µm and 0.35µm gate SOI CMOS is experimentally studied, using supply current measurement of inverter chains as test structures. The threshold voltage shift is obtained from the measurement of the leak currents in DC and high frequency condition. For a large supply voltage the electron-hole generation current becomes dominant, resulting in lowered threshold voltage, while the threshold voltage becomes higher than DC case for a low supply voltage. A reasonable relation of the threshold voltage shift and average electric field in the channel is obtained in this study. This method will be useful as a measure of "substrate current" for floating body SOI CMOS.

In this paper, bifurcation and chaotic behavior which occur in simple looped MOS inverters with high speed operation are described. The most important point in this work is to change a nonlinear transfer characteristic of a MOS inverter to the nonlinearity generating a chaos. Three types of circuits which include four, three and one MOS inverters, respectively, are proposed. A switched capacitor (SC) circuit to operate sampling holding is added in the loop in each of the circuits. The bifurcation and chaotic behavior have been found along with a variation of an external input, and/or a sampling clock frequency. The bifurcation and chaotic behavior of the proposed simple looped MOS inverters are verified by employing SPICE circuit simulator as well as the experiments. For the first type of four looped CMOS inverters, Lyapunov exponent λ which has the positive regions for the chaotic behavior can be calculated by use of the fitting nonlinear function synthesized from two sigmoid functions. For the second type of three looped CMOS inverters and the third type of one looped MOS inverter, the nonlinear charge/discharge characteristics of the hold capacitor in the SC circuit is utilized efficiently for forming the nonlinearity generating the bifurcation and chaotic behavior. Their bifurcation can be generated by the sampling clock frequency parameter which is controlled easily.

A capacitor-error-free SC voltage inverter with zero sensitivity to element-value variations is proposed. By virtue of the capacitor-error-free property, this SC voltage inverter is free from the capacitor mismatch. The performance of this SC voltage inverter has been confirmed from both the simulation and experiment.

The development of highly accurate and durable control system is becoming a must for todays high performance automobiles. For example, it is necessary to up-grade todays materials and methods creating more sensitive sensors, higher speed processors and more accurate actuators, while also being more durable. Thus, the development of a CMOS time-to-digital converter LSI with half-nanosecond resolution, which controls only pulse signals was achieved by employing 1.5 µm CMOS technology. The new signal detecting circuit, 1.1 mm2 in size, converts time to numerical values over a wide measurement range (13 bits). The compact digital circuit employs a newly developed "ring gate delay system". Within the LSI the fully digital circuit is highly durable. This allows it to be utilized even under severe conditions (for example an operating ambient temperature of 130). In order to measure time accurately, a method of correcting the variation of measurement time data employing a real-time conversion fully digital circuit is described. This method allows for fully automatic correction with a microcomputer, so no manual adjustment is required. In addition to sensor circuit applications, the LSI has great potential for Application Specific Integrated Circuit, (ASIC) such as a function cell with is a completely new method of measuring time.

This paper describes the dependence of the delay time of a CMOS/SIMOX inverter on the gate-overlap capacitance. An analytical delay-time equation for the CMOS/SIMOX inverter, which includes the gate-overlap capacitance, is derived. This equation shows that the feed-forward effect dominates the characteristics of inverters with a small fanout. The validity of the delay-time equation is confirmed by the comparison to experimental measurements of 0.4-µm CMOS/SIMOX devices. Moreover, a sensitivity analysis shows that it is very important to reduce the gate-drain overlap capacitance for fabricating high-speed scaled-down CMOS/SIMOX devices.