In renewable power generators, because of high initial cost and duty cycle of systems, efficiency parameter has an important place. For this reason, line frequency controlled multilevel inverters are one of most proper choices for renewable power converters. Among these, diode-clamped multilevel inverter structures are one of most important and best efficient inverters. In this paper, a simple diode-clamped equivalent circuit for exploring the efficiency under resistive loads is proposed, and based on this simple circuit, the on-state power dissipation in improved and original diode-clamped multilevel inverter under resistive loads is analyzed. Then, comparative efficiency equations are extracted for inverters that use metal oxide semiconductor field-effect transistors (MOSFETs) and other p-n junction as switches. These equations enable us to have a better idea of conducting power dissipation in diode-clamped and help us to choose appropriate switches for having a lower on-state power dissipation. Some cases are studied and in the end it is proven that the calculated efficiency under resistive load is a boundary for inductive load with the same impedance in diode-clamped inverter with p-n junction switches. This means that calculating the efficiency under resistive loads enables us to approximately predict efficiency under inductive loads.

An inverter is a circuit which outputs ¬ x1, ¬ x2, ..., ¬ xn for any Boolean inputs x1, x2, ..., xn. We consider constructing an inverter with AND gates and OR gates and a few NOT gates. Beals, Nishino and Tanaka have given a construction of an inverter which has size O(nlog n) and depth O(log n) and uses ⌈ log (n+1) ⌉ NOT gates. In this paper we give a construction of an inverter which has size O(n) and depth log 1+o(1)n and uses log 1+o(1)n NOT gates. This is the first negation-limited inverter of linear size using only o(n) NOT gates. We also discuss implications of our construction for negation-limited circuit complexity.

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.

This study involves implementing an intelligent controller using the fuzzy control algorithm to minimize cold weld and splash in inverter AC spot welding. This study presents an experimental curve of a welding output current and the maximum value of the Instantaneous Heating Rate (IHRmax) using the contact diameter of an electrode as the parameter. It also presents the experimental curve of a welding output current and the slope (S) of the instantaneous dynamic resistance using the instantaneous contact area of an electrode as the parameter. To minimize cold weld and splash, this study proposes an intelligent controller that controls the optimum welding current in real time by estimating the contact diameter of an electrode and the contact area of the initial welding part.

This paper presents a 1 V operating fully differential OTA using NMOS inverters in place of the traditional differential pair. To obtain high gain, a two-stage configuration is used in which the first stage has feedforward paths to cancel the common-mode signal, and the second stage has common-mode feedback paths to stabilize the output common-mode voltage. The proposed OTA was fabricated by an 0.18 µm CMOS technology. Measured gain is 40 dB and GBW is 10 MHz, in addition to differential output voltage swing of 1.8 Vp - p. It is confirmed that the proposed OTA can operate from 1 V power supply and has very large output swing capability even in a 1 V operation. The proposed OTA configuration contributes to a solution to the low power supply voltage issue in scaled CMOS analog circuits.

A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18 µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3 V to 1.8 V. The current consumption of voltage detection, standby current, is changed from 65 pA for Vin = 0.3 V to 5.5 µA for Vin = 1.8 V. The thermal characteristics from 250 K to 400 K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4 ppm/K and that in saturation region is 10 ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.

We fabricated both thin film transistors (TFTs) and diodes using zinc oxide (ZnO) and pentacene, and investigated their basic characteristics. We found that field-effect mobility is influenced by the interface state between the semiconductor and dielectric layers. Furthermore, the complementary metal oxide semiconductor (CMOS) inverter using a p-channel pentacene field-effect transistor (FET) and an n-channel ZnO FET showed a relatively high voltage gain (8-12) by optimizing the device structure. The hybrid complementary inverters described here are expected for application in flexible displays, radio frequency identification cards (RFID) tags, and others.

This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.

This paper presents a very wideband active RC polyphase filter (ARCPF). We propose a unit section of the ARCPF, which is an ordinary RCPF followed by opamps with parallel RC feedback. In the proposed unit section, pole and zero can be assigned independently. By using the unit ARCPFs, a very wideband image rejection filter can be realized by cascading the sections, which can greatly reduce the element value spread. To realize this, CMOS inverter based fully differential OTA which can operate under low supply voltage is also presented. This paper describes a six-stage active RC polyphase filter with 1-100 MHz passband in 0.18 µm CMOS technology.

This study presents a class of miniature parallel-coupled bandpass filters with good selectivity and stopband rejection. Capacitive terminations are introduced to the conventional anti-parallel coupled-lines, and lumped-element K-inverters are employed, to achieve both size reduction and spurious suppression. Additionally, the capacitive cross-coupling effect can be introduced to obtain three transmission zeros to enhance the selectivity. Suitable equivalent-circuit models, along with design formulae, are also established. Specifically, via design examples, this work demonstrates the feasibility of proposed filter structures in microstrip configuration. Compared to the conventional parallel-coupled filters, the proposed filters exhibit over 60% size reduction, improved selectivity, and wider stopbands up to four times the center frequency.

Synchronization has gained attention in science recently. In electrical engineering, a power network requires generators and loads to be in synchronization. The increase in distributed dc power sources without sophisticated controls has made synchronization more difficult. This paper proposes a synchronous inverter designed for linking distributed power sources within a power network. The linkage inverters should have high confidential characteristics to keep the network stable. The frequency and phase synchronization between synchronous generators in power network has been acheived through power transmission systems. The synchronous inverters contribute in the development of the sophisticated power networks by providing distributed power sources that maintain synchronous operation.

In this paper, class DE inverter with second order constant K band-pass filter is proposed. In the proposed inverter, the band-pass filter is used instead of the resonant filter in class DE inverter presented at the previous papers. By using band-pass filter, two important results can be gotten. One is the sensitivity of the output voltage to the operating frequency is suppressed by using band-pass filter. The other is that zero voltage switching operation appears when the operating frequency is lower than the nominal frequency. Moreover, it keeps the advantage of class DE inverter with resonant filter, that is, high power conversion efficiency under high frequency operation because of class E switching. The laboratory experiments achieve 90.4% power conversion efficiency under 1.98 W output power and 1.0 MHz operation.

Organic static induction transistors (OSITs) with vertical structure have advantage of lower operational voltage compared to the organic field effect transistors with conventional lateral structure. In this study, OSITs based on pentacene films were applied to fabricate the organic inverters which can operate at low voltage. The experimental results demonstrate that organic inverters based on the OSITs show basic transfer characteristics and a low operational voltage of 2 V.

In this paper, a new dimming algorithm for the electronic ballast of an electrodeless fluorescent lamp is proposed. The proposed method is based on the burst dimming method that controls the duty ratio for the two switches of the electronic ballast by intermittently modulated pulse signal. This paper presents a fully digital circuit using an erasable programmable logic device (EPLD). To verify the validity of the proposed method, the implemented control circuit was applied to the electronic ballast for a 100 W electrodeless fluorescent lamp. As a result, a dimming method with a wide illumination range from 5 to 100% was obtained.

A novel method is proposed to synthesize dual-band bandpass filters (BPFs) from a prototype lowpass filter. By implementing successive frequency transformations and circuit conversions, a new filter topology is obtained which consists of only admittance inverters and series or shunt resonators, and is thereby easy to be realized by using conventional distributed elements. A microstrip dual-band BPF with central frequencies of 1.8 GHz and 2.4 GHz is designed and fabricated using microstrip lines and stubs. The simulated and measured results show a good agreement and validate thereby the proposed theory.

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

Novel microstrip dual-band bandpass filters with controllable fractional bandwidths and good in-between isolation are presented and implemented. A half-wavelength stepped-impedance resonator is firstly characterized, aiming at producing the two resonant frequencies at 2.4 and 5.2 GHz. Two types of coupled microstrip lines in the parallel and anti-parallel formats are then investigated in terms of unified equivalent J-inverter network. Extensive results are derived to quantitatively show their distinctive frequency-distributed coupling performances under different coupling lengths. The coupling degrees of these two coupled lines at the two resonances are properly adjusted to achieve the dual-passband response with varied or tunable bandwidths. In addition, the parallel coupled line is modeled to bring out a transmission zero between the two resonances so as to achieve the good in-between isolation. The three two-stage bandpass filters are initially designed to exhibit their dual-band response with changeable dual-band bandwidths. A three-stage dual-band filter is in final optimally designed and its predicted performance is confirmed in experiment.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

This paper proposes a backlight module which drives multiple cold-cathode fluorescent lamps (CCFLs) with a current mirror technique to equalize the driving current for each lamp. We first adopt a half-bridge parallel-resonant inverter as the main circuit and use a single-input, multiple-output transformer to drive the multi-CCFLs. Next, we introduce current-mirror circuits to create a new current-sharing circuit, in which its current reference node and the parallel-connected multi-load nodes are used to accurately equalize all CCFLs' driving current. This will balance each lamp's brightness and, consequently, improve the picture display quality of the related liquid crystal display (LCD). This paper details the design concept for each component value with the assistance of an actual design example. The results of the example are examined with its actual measurements, which consequently verify the correctness of the proposed control strategy.