IEICE TRANSACTIONS on Electronics
An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation
Summary :
This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-µm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181fJ/Conv.-step at a 25kS/s sampling rate when the supply voltage VDD is 1.2V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.12 pp.1331-1334
- Publication Date
- 2016/12/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.1331
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
Authors
Guan-Wei JEN
Faraday Technology Corp.
Wei-Liang LIN
National Chung Hsing University
Keyword
Latest Issue
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Guan-Wei JEN, Wei-Liang LIN, "An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 12, pp. 1331-1334, December 2016, doi: 10.1587/transele.E99.C.1331.
Abstract: This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-µm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181fJ/Conv.-step at a 25kS/s sampling rate when the supply voltage VDD is 1.2V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.1331/_p
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@ARTICLE{e99-c_12_1331,
author={Guan-Wei JEN, Wei-Liang LIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation},
year={2016},
volume={E99-C},
number={12},
pages={1331-1334},
abstract={This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-µm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181fJ/Conv.-step at a 25kS/s sampling rate when the supply voltage VDD is 1.2V.},
keywords={},
doi={10.1587/transele.E99.C.1331},
ISSN={1745-1353},
month={December},}
Copy
TY - JOUR
TI - An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1331
EP - 1334
AU - Guan-Wei JEN
AU - Wei-Liang LIN
PY - 2016
DO - 10.1587/transele.E99.C.1331
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2016
AB - This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-µm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181fJ/Conv.-step at a 25kS/s sampling rate when the supply voltage VDD is 1.2V.
ER -
English
