In this paper, we describe two approaches to optimize the Phase-Mode pipelined parallel multiplier. One of the approaches is reforming a data distribution for an AND array, which is named the hybrid structure. Another method is applying a Booth encoder as a substitute of the AND array in order to generate partial products. We design a 2-bit 2-bit Phase-Mode Booth encoder and test the circuit by the numerical simulations. The circuit consists of 21 ICF gates and operates correctly at a throughput of 37.0 GHz. The numbers of Josephson junctions and the pipelined stages in each scale of multipliers are reduced remarkably by using the encoder. According to our estimations, the Phase-Mode Booth encoder is the effective component to improve the performance of large-scale parallel multipliers.

A Radial Line Slot Antenna (RLSA) is a planar antenna for DBS reception. It is a kind of slotted waveguide arrays. The conductor loss is so small that high efficiency is expected irrespective of the aperture diameter. On the other hand, since a RLSA utilizes the traveling waves, the frequency bandwidth is limited by the long line effect, particularly for a larger antenna. A new Wide-Band RLSA (WB-RLSA) is proposed which halves the waveguide length and widens the frequency bandwidth. This paper presents the design and experimental results of a model antenna. A gain of 33.7dBi is measured at the edge of 800MHz bandwidth and its high potential is demonstrated.