Low-temperature poly-Si thin film transistor with gate-overlapped LDD (GOLD) structure was fabricated. Reliability was evaluated using electrical stress method comparing conventional LDD and single drain structures. As previous researchers have reported, we have confirmed that the degradation of ON current and the field effect mobility was very small compared to conventional LDD or non-LDD structures. We have analyzed the reliability of the GOLD TFT using two-dimensional device simulator. We have clarified that vertical negative field plays a dominant role for improving the reliability in the GOLD TFT. Impact ionization occurs far from the interface between the oxide and poly-silicon by the vertical negative field. GOLD structure is promising for the realization of system on panel.