In this paper, we propose the CMOS implementation of neuron models for an artificial auditory neural network. We show that when voltage is added directly to the control terminal of the basic circuit of the hardware neuron model, a change in the output firing is observed. Next, based on this circuit, a circuit that changes with time is added to the control terminal of the basic circuit of the hardware neuron model. As a result, a neuron model is constructed with ON firing, adaptation firing, and repetitive firing using CMOS. Furthermore, an improved circuit of a neuron model with OFF firing using CMOS which has been improved from the previous model is also constructed.

A number of studies have recently been published concerning chaotic neuron models and asynchronous neural networks having chaotic neuron models. In the case of large-scale neural networks having chaotic neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, due to the high speed and high integration of analog circuits. In the present study, we discuss the circuit structure of a chaotic neuron model, which is constructed on the basis of the mathematical model of an asynchronous chaotic neuron. We show that the pulse-type hardware chaotic neuron model can be constructed on the basis of the mathematical model of an asynchronous chaotic neuron. The proposed model is an effective model for the cell body section of the pulse-type hardware chaotic neuron model for ICs. In addition, we show the bifurcation structure of our composed model, and discuss the bifurcation routes and return maps thereof.