As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC π load. By representing the short-circuit current and the current flowing in the resistance of a CRC π load by piece-wise linear functions, a closed-form formula is derived. On the gate delay the error of our formula is less than 8% from SPICE in our experiments. These formulas will contribute to faster estimation of circuit speed and power dissipation of VLSI chips on timing level simulators.