In this study, I have numerically investigated the temperature distribution of n-type Si Nano Wire MOS Transistor induced by the self-heating effect by using a 3-D device simulator. The dependencies of temperature distribution within the Si Nano Wire MOS Transistor on both its gate length and width of the Si nano wire were analyzed. First, it is shown that the peak temperature in Si Nano Wire MOS Transistor increases by 100 K with scaling the gate length from 54 nm to 14 nm in the case of a 50 nm width Si nano wire. Next, it is found that the increase of its peak temperature due to scaling the gate length can be suppressed by scaling the size of the Si nano wire, for the first time. The peak temperature suppresses by 160 K with scaling the Si nano wire width from 50 nm to 10 nm in the case of a gate length of 14 nm. Furthermore, the heat dissipation in the gate, drain, and source direction are analyzed, and the analytical theory of the suppression of the temperature inside Si Nano Wire MOSFET is proposed. This study shows very useful results for future Si Nano Wire MOS Transistor design for suppressing the self-heating effect.

High-frequency characteristics of SiGe heterojunction bipolar transistors with different emitter sizes are studied based on pulsed measurements. Because the self-heating effect in transistors will enhance the Kirk effect, as the devices operate in high current region, the measured cutoff frequency and maximum oscillation frequency decrease with measurement time in the pulsed duration. By analyzing the equivalent small-signal device parameters, we know the reduction of cutoff frequency and maximum oscillation frequency is attributed to the reduction of transconductance and the increase of junction capacitances for fixed base-emitter voltage, while it is only attributed to the degradation of transconductance for fixed collector current. Besides, the degradation of high-frequency performance due to self-heating effect would be improved with the layout design combining narrow emitter finger and parallel-interconnected subcells structure.