As is well known in the design of transformer isolated converters, the transformer leakage inductance causes a large voltage overshoot on the secondary side switching nodes at every switch transition, unless measures are taken to limit the peak voltage stress. Since the peak voltage stress in smart-power integrated converters, where the power devices are integrated on the same die as the controlling logic and supporting circuits, is the major determining factor for the required silicon area for the implementation, this is a major roadblock for the affordable integration of this type of converter. Therefore, any cost-effective smart-power synchronous rectifier requires a voltage clamping circuit that minimizes the voltage stress, while still maintaining the potential advantages of smart-power converters, i.e. minimizing the number and size of the discrete components in the converter. We present an integrated asynchronous active clamping circuit, that can clamp the overshoot voltage to arbitrary voltages while optimizing the efficiency by only being active when required. Because of the asynchronous operation, the size of the required external components is minimized. Measurements on the smart-power IC implementation of the asynchronous active clamp circuit combined with a secondary side synchronous rectifier for a 1 MHz full bridge converter confirm the reduction in voltage stress and the optimization of the efficiency.

We suggest a novel digitally-controlled SMPS using a high-resolution DPWM generator. In the proposed circuit, the duty ratio of the DPWM is determined by the voltage slope control of an internal capacitor using a pseudo relaxation-oscillation technique. This new control method has a simpler structure, and consumes less power compared to a conventional digitally-controlled SMPS. Therefore, the proposed circuit is able to operate at a high switching frequency (1 MHz10 MHz) obtained from a relatively low internal operating frequency (10 MHz100 MHz) with a small area. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit, including the output buffer driver, is 15 mA at 10 MHz switching frequency. The proposed circuit is designed to supply a maximum 1A with maximum DPWM duty ratio of 90%. The output voltage ripple is 7 mV at 3.3 V output voltage. To verify the operation of the proposed circuit, we performed a simulation with Dongbu Hitek BCD 0.35 µm technology.

All power electronic circuits with state feedback controlled switching can be described as nonlinear time-varying dynamical systems. The occurrence of chaos--where the ripple waveforms become aperiodic--is common in such systems. It is shown here that this natural phenomenon may be effectively used in minimizing electromagnetic interference problems in power electronic circuits. This is because converters operating chaotically tend to spread the spectrum, thereby reducing the interference power at any target frequency. We also present the ways of calculating the average values of state variables and the power spectrum under chaotic operation.