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[Keyword] state reduction(4hit)

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  • Genetic State Reduction Method of Incompletely Specified Machines

    Masaki HASHIZUME  Teruyoshi MATSUSHIMA  Takashi SHIMAMOTO  Hiroyuki YOTSUYANAGI  Takeomi TAMESADA  Akio SAKAMOTO  

     
    PAPER-Graphs and Networks

      Vol:
    E87-A No:6
      Page(s):
    1555-1563

    A new state reduction method of incompletely specified sequential machines is proposed in this paper. The method is based on a genetic algorithm implementing a dormant mechanism. MCNC benchmark machines are simplified by using this method to evaluate the method. The experimental results show that machines of almost the same number of states as the minimum ones can be derived by this method.

  • Exploiting Symmetric Relation for Efficient Feature Interaction Detection

    Masahide NAKAMURA  Tohru KIKUNO  

     
    PAPER-Computer Networks

      Vol:
    E82-D No:10
      Page(s):
    1352-1363

    Feature interaction detection determines whether interactions occur or not between the new and existing telecommunication services. Most of conventional detection methods on state transition model utilize an exhaustive search. The exhaustive search is fundamentally very powerful in the sense that all interactions are exactly detected. However, it may suffer from the state explosion problem due to the exponential growth of the number of states in the model when the number of users and the number of features increase. In order to cope with this problem, we propose a new detection method using a state reduction technique. By means of a symmetric relation, called permutation symmetry, we succeed in reducing the size of the model while preserving the necessary information for the interaction detection. Experimental evaluation shows that, for practical interaction detection with three users, the proposed method achieves about 80% reduction in space and time, and is more scalable than the conventional ones especially for the increase of the number of users in the service.

  • Heuristic State Reduction Methods of Incompletely Specified Machines Preceding to Satisfy Covering Condition

    Masaki HASHIZUME  Takeomi TAMESADA  Takashi SHIMAMOTO  Akio SAKAMOTO  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E81-A No:6
      Page(s):
    1045-1054

    This paper presents two kinds of simplification methods for incompletely specified sequential machines. The strategy of the methods is that as many states in original machines are covered in the simplification processes as possible. The purpose of the methods is to derive a simplified machine having either the largest maximal compatible set or its subset. With the methods, one of the minimal machines can not be always derived, but a near-minimal machine can be obtained more quickly with less memory, since they need not derive all the compatible sets. In this paper, the effectiveness of the methods is checked by applying them to simplification problems of incompletely specified machines generated by using random numbers, and of the MCNC benchmark machines. The experimental results show that our methods can derive a simplified machine quickly, especially for machines having a great number of states or don't care rate.

  • An lterative Improvement Method for State Minimization of Incompletely Specified Finite State Machines

    Hiroyuki HIGUCHI  Yusuke MATSUNAGA  

     
    PAPER-Logic Design

      Vol:
    E80-D No:10
      Page(s):
    993-1000

    This paper proposes a heuristic algorithm for state minimization of incompletely specified finite state machines (FSMs). The strategy is similar to that in ESPRESSO, a wellknown heuristic algorithm for two-level logic minimization. It consists of generating an initial solution, the set of maximal compatibles, and attempting to apply a series of transformations to the solution. The main transformation is to reduce each compatible in the solution and delete unnecessary compatibles by iterative improvements. Other transformations, such as expansion and merging of compatibles, are also introduced for further reduction. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a Binary Decision Diagram. Experimental results show that the proposed method finds better solutions in shorter CPU times for most of the examples than conventional methods.