In this paper, we discuss an abstraction method for Petri nets based on an equivalence of firing sequences of a specified subnet or a specified subset of transitions. Specifically, a method is presented to generate an equivalent net which preserves firing sequences of a specified subnet or a specified subset of transitions. The abstraction can be applied to an efficient behavioral analysis of concurrent systems constructed by composition of modules such as communication networks and Flexible Manufacturing Systems (FMS).

The symbolic model checking algorithm was proposed for the efficient verification of sequential circuits. In this paper, we show that this algorithm is applicable to the verification of concurrent systems described by finite capacity Petri nets. In this algorithm, specifications of the system are given in the form of temporal logic formulas, and the algorithm checks whether these formulas hold in the state space. All logical operations are performed on Binary Decision Diagrams. Since the algorithm does not enumerating each state, the problem of state space explosion can be avoided in many cases.

In this paper, an approach to derive a logic function of asynchronous circuits from a graph-based model called Signal Transition Graphs (STG) is discussed. STG's are Petri nets, whose transitions are interpreted as a signal transition on the circuit inputs or gate outputs, and its marking represents a binary state of the circuit. STG's can represent a behavior of circuit, to derive logic functions, however, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seem as a parallel algorithm for deriving a logic function.

This paper proposed a practical method of program validation for state-based reactive concurrent systems. The proposed method is of particular relevance to plant control systems. Plant control systems can be represented by extended state transition systems (e.g., communicating asynchronous transition systems). Our validation method is based on state space analysis. Since naive state space analysis causes the state explosion problem, techniques to ease state explosion are necessary. One of the most promising techniques is the partial order method. However, these techniques usually require some structural assumptions and they are not always effective for actual control systems. Therefore, we claim integration and harmonization of verification (i.e., state space analysis based on the partial order method) and simulation (i.e., conventional validation technique). In the proposed method, verification is modeled as exhaustive simulation over the state space, and two types of simulation management techniques are introduced. One is logical selection (pruning) based on the partial order method. The other is heuristic selection based on priority (a priori precedence) specified by the user. In order to harmonize verification (logical selection) and conventional simulation (heuristic selection), we propose a new logical selection mechanism (the default priority method). The default priority method which prunes redundant state generation based on default priority is in harmony with heuristic selection based on the user's priority. We have implemented a practical validation tool, Simulation And Verification Environment for Reactive Concurrent Systems (SAVE/RCS), and applied it to chemical plant control systems.

State space explosion is a serious problem in analyzing discrete event systems that allow concurrent occurring of events. A new method is proposed for generating reduced state spaces of systems. This method is an improvement of Valmari's stubborn set method. The generated state space preserves liveness, livelocks, and terminal states of the ordinary state space. Petri nets are used as a model of systems, and a method is shown for generating a reduced state space from a given Petri net.

It is an important problem whether or not we can reject the disturbances from distributed parameter circuit. In order to analyze this problem structurally, it is necessary to investigate the basic equation of distributed parameter circuit in the framework of state space. Since the basic equation has two parameters for time and space, the state value belongs to an infinite-dimensional space. In this paper, the disturbance-rejection problems with incomplete state feedback and/or incomplete state feedback and feedforward for infinite-dimensional systems are studied in the framework of geometric approach. And under certain assumptions, necessary and/or sufficient conditions for these problems to be solvable are proved.

In this paper, we propose a plausible software reliability growth model by applying a mathematical technique of stochastic differential equations. First, we extend a basic differential equation describing the average behavior of software fault-detection processes during the testing phase to a stochastic differential equation of ItÔ type, and derive a probability distribution of its solution processes. Second, we obtain several software reliability measures from the probability distribution. Finally, applying a method of maximum-likelihood we estimate unknown parameters in our model by using available data in the actual software testing procedures, and numerically show the stochastic behavior of the number of faults remaining in the software system. Further, the model is compared among the existing software reliability growth models in terms of goodness-of-fit.

A simple inequality that guarantees stability of perturbed linear state space models is proposed. It is shown that the result is superior to some existing result in sharpness and possesses some advantageous aspects.

This paper treats the problem of realizing high speed 2-D denominator separable digital filters. Partitioning a 2-D data plane into square blocks, filtering proceeds block by block sequentially. A fast intra-block parallel processing method was developed using block state space realization, which allows simultaneous computation of all the next block states and the outputs of one block. As the block state matrix of the filter has high sparsity, the rows and columns are interchanged respectively to reduce the matrix size. The filter is implemented by a multiprocessor system, where for each matrix's row one processor is assigned to perform the row-column vector multiplication. All processors wirk in synchronized fashion. Number of processors of this implementation are equal to the number of rows of the reduced state matrix and throughput is raised with block lengths.