New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. The modeling approaches for various emerging SOI technologies are discussed in this paper.

Enhancement of inversion-layer mobility and inversion-layer capacitance becomes more important in realizing scaled CMOS, from both viewpoints of higher performance and lower power consumption. This paper presents an engineering scenario of the subband structure in inversion layer for the enhancement of inversion-layer mobility and capacitance in MOSFETs. A key factor for the electron mobility enhancement is to increase the energy difference in the subband energy between the two-fold and the four-fold valleys and the resultant electron occupancy of the two-fold valleys. The electrical characteristics of two device structures based on this subband engineering, strained-Si MOSFETs and ultra-thin SOI MOSFETs, are studied. Also, it is shown that the reduction in SOI films down to less than inversion-layer thickness of bulk MOSFETs is an effective way to increase inversion-layer capacitance.

We have developed advanced SOI n- and p-MOSFETs with strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separation-by-implanted-oxygen) technology. The characteristics of this strained-SOI substrate and electrical properties of strained-SOI MOSFET's have been experimentally studied. Using strained-Si/relaxed-SiGe epitaxy technology and usual SIMOX process, we have successfully formed the layered structure of fully-strained-Si (20 nm)/fully-relaxed-SiGe film (290 nm) on uniform buried oxide layer (85 nm) inside SiGe layer. Good drain current characteristics have been obtained in strained-SOI MOSFET's. It is found that both electron and hole mobility is enhanced in strained-SOI MOSFET's, compared to the universal mobility in an inversion layer and the mobility of control SOI MOSFET's. These mobility enhancement factors are almost the same as the theoretical results.