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[Keyword] sum-product algorithm(9hit)

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  • Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors

    Beomkyu SHIN  Hosung PARK  Jong-Seon NO  Habong CHUNG  

     
    LETTER-Fundamental Theories for Communications

      Vol:
    E94-B No:8
      Page(s):
    2375-2377

    In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.

  • Characterization of Factor Graph by Mooij's Sufficient Condition for Convergence of the Sum-Product Algorithm

    Tomoharu SHIBUYA  

     
    LETTER-Coding Theory

      Vol:
    E93-A No:11
      Page(s):
    2083-2088

    Recently, Mooij et al. proposed new sufficient conditions for convergence of the sum-product algorithm, and it was also shown that if the factor graph is a tree, Mooij's sufficient condition for convergence is always activated. In this letter, we show that the converse of the above statement is also true under some assumption, and that the assumption holds for the sum-product decoding. These newly obtained fact implies that Mooij's sufficient condition for convergence of the sum-product decoding is activated if and only if the factor graph of the a posteriori probability of the transmitted codeword is a tree.

  • A Low-Complexity and High-Performance 2D Look-Up Table for LDPC Hardware Implementation

    Jung-Chieh CHEN  Po-Hui YANG  Jenn-Kaie LAIN  Tzu-Wen CHUNG  

     
    LETTER-Coding Theory

      Vol:
    E92-A No:11
      Page(s):
    2941-2944

    In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.

  • Data Fusion of TOA and AOA Measurements for Target Location Estimation in Heterogeneous Wireless Sensor Networks Using Factor Graphs

    Jung-Chieh CHEN  

     
    LETTER-Digital Signal Processing

      Vol:
    E92-A No:11
      Page(s):
    2927-2931

    This paper considers the problem of target location estimation in heterogeneous wireless sensor networks and proposes a novel algorithm using a factor graph to fuse the heterogeneous measured data. In the proposed algorithm, we map the problem of target location estimation to a factor graph framework and then use the sum-product algorithm to fuse the heterogeneous measured data so that heterogeneous sensors can collaborate to improve the accuracy of target location estimation. Simulation results indicate that the proposed algorithm provides high location estimation accuracy.

  • High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving

    Naoya ONIZAWA  Takahiro HANYU  Vincent C. GAUDET  

     
    PAPER-Electronic Circuits

      Vol:
    E92-C No:6
      Page(s):
    867-874

    This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 nm CMOS technology, at a comparable BER.

  • A Novel Strategy Using Factor Graphs and the Sum-Product Algorithm for Satellite Broadcast Scheduling Problems

    Jung-Chieh CHEN  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E91-B No:3
      Page(s):
    927-930

    This paper presents a low complexity algorithmic framework for finding a broadcasting schedule in a low-altitude satellite system, i.e., the satellite broadcast scheduling (SBS) problem, based on the recent modeling and computational methodology of factor graphs. Inspired by the huge success of the low density parity check (LDPC) codes in the field of error control coding, in this paper, we transform the SBS problem into an LDPC-like problem through a factor graph instead of using the conventional neural network approaches to solve the SBS problem. Based on a factor graph framework, the soft-information, describing the probability that each satellite will broadcast information to a terminal at a specific time slot, is exchanged among the local processing in the proposed framework via the sum-product algorithm to iteratively optimize the satellite broadcasting schedule. Numerical results show that the proposed approach not only can obtain optimal solution but also enjoys the low complexity suitable for integral-circuit implementation.

  • Transformation of a Parity-Check Matrix for a Message-Passing Algorithm over the BEC

    Naoto KOBAYASHI  Toshiyasu MATSUSHIMA  Shigeichi HIRASAWA  

     
    PAPER

      Vol:
    E89-A No:5
      Page(s):
    1299-1306

    We propose transformation of a parity-check matrix of any low-density parity-check code. A code with transformed parity-check matrix is an equivalent of a code with the original parity-check matrix. For the binary erasure channel, performance of a message-passing algorithm with a transformed parity-check matrix is better than that with the original matrix.

  • Construction of Cyclic Codes Suitable for Iterative Decoding via Generating Idempotents

    Tomoharu SHIBUYA  Kohichi SAKANIWA  

     
    PAPER-Coding Theory

      Vol:
    E86-A No:4
      Page(s):
    928-939

    A parity check matrix for a binary linear code defines a bipartite graph (Tanner graph) which is isomorphic to a subgraph of a factor graph which explains a mechanism of the iterative decoding based on the sum-product algorithm. It is known that this decoding algorithm well approximates MAP decoding, but degradation of the approximation becomes serious when there exist cycles of short length, especially length 4, in Tanner graph. In this paper, based on the generating idempotents, we propose some methods to design parity check matrices for cyclic codes which define Tanner graphs with no cycles of length 4. We also show numerically error performance of cyclic codes by the iterative decoding implemented on factor graphs derived from the proposed parity check matrices.

  • A Coded Modulation Scheme Based on Low Density Parity Check Codes

    Tadashi WADAYAMA  

     
    LETTER-Coding Theory

      Vol:
    E84-A No:10
      Page(s):
    2523-2527

    A coded modulation scheme based on a low density parity check (LDPC) code is presented. A modified sum-product algorithm suitable for the LDPC-coded modulation scheme is also devised. Several simulation results show the excellent decoding performance of the proposed coding scheme. For example, an LDPC-coded 8PSK scheme of block length 3976 symbols achieves the symbol error probability 10-5 at only 1.2 dB away from the Shannon limit of the channel.