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[Keyword] tracing(83hit)

81-83hit(83hit)

  • A New High-Speed Boundary Matching Algorithm for Image Recognition

    Albert T. P. SO  W. L. CHAN  

     
    PAPER

      Vol:
    E77-D No:11
      Page(s):
    1219-1224

    The Paper describes a comprehensive system for image recognition based on the technique of boundary spline matching. It can be used to accurately compare two objects and determine whether they are identical or not. The result is extremely satisfactory for comparing planar objects as revealed from the illustrative example presented in this paper. In real practice, images of the same scene object can easily be considered as belonging to different objects if the objects are viewed from different orientations and ranges. Thus, image recognition calls for choosing the proper geometric transformation functions to match images as the initial step so that recognition by template matching can be done as the second step. However, there are a large variety of transformation functions available and the subsequent evaluation of transformation parameters is a highly nonlinear optimisation procedure which is both time consuming and not solution guaranteed, making real-time estimation impossible. This paper describes a new method that represents the boundary of each of two image objects by B-splines and matches the B-splines of two image objects to determine whether they belong to the same scene object. The algorithm developed in this paper concentrates on solving linear simultaneous equations only when handling the geometric transformation functions, which takes almost negligible computational time by using the standard Gaussian Elimination. Representation of the image boundary by B-splines provides a flexible and continuous matching environment so that the level of accuracy can be freely adjusted subject to the requirement of the user. The non-linear optimisation involves only one parameter, i.e. the starting point of each boundary under B-spline simulation, thus guaranteeing a very high speed computational system. The real time operation is deemed possible even there is a wide choice of proper transformation functions.

  • E-Beam Static Fault Imaging with a CAD Interface and Its Application to Marginal Fault Diagnosis

    Norio KUJI  Kiyoshi MATSUMOTO  

     
    PAPER

      Vol:
    E77-C No:4
      Page(s):
    552-559

    A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.

  • Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System

    Katsuyoshi MIURA  Koji NAKAMAE  Hiromu FUJIOKA  

     
    PAPER-Computer Aided Design (CAD)

      Vol:
    E77-A No:3
      Page(s):
    539-545

    An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.

81-83hit(83hit)