A novel delivery management system using a new lot sampling scheduling (LSS) method has been developed. The method involves the concepts of "virtual line" and "marker lot," and the system consists of an on-line scheduler executing short-period scheduling for lot-tracking and an off-line scheduler executing long-period scheduling for delivery date simulation. The LSS method can hugely increase the maximum number of lots to simulate the delivery date and also control TAT more effectively compared to conventional dynamic scheduling. Lot progress is controlled by varying the resource allocation ratio for each virtual line. This method is effective for precise delivery date control of lots with various priorities in ASIC production or development lines.

New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.