In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.

A low energy plasma based on an electron discharge was investigated for the pre-epi clean of silicon wafers and for plasma enhanced homo and hetero epitaxial growth of Si and SiGe layers. VS were produced in a short, completely dry process sequence consisting of LEPC and LEPECVD only. The wafer/epilayer interface obtained in this process sequence was suitable to grow high quality VS with low surface roughness and dislocation densities. Based on this process and its implementation in a 200/300 mm single wafer cluster tool, a high volume and economical production of VS seems possible.