A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we introduce the 1(1/2)-track switch torus array by changing the connections in 1(1/2)-track switch mesh array, and we apply our approximate reconfiguration algorithm to the torus array. We describe the reconfiguration strategy for the 1(1/2)-track switch torus array and its realization using WSI, especially 3-dimensional realization. A hardware realization of the algorithm is proposed and simulation results about the array reliability are shown. These imply that a self-reconfigurable system with no host computer can be realized using our method, hence our method is effective in enhancing the run-time reliability as well as the fabrication-time yield of processor arrays.

In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.

We gave in [1] the software and hardware algorithms for reconfiguring 1 1/2-track switch 2-D mesh arrays with faults of processing elements, avoiding them. This paper shows an implementation of the hardware algorithm using an FPGA device, and by the logical simulation confirms the correctness of the behavior and evaluates reconfiguration time. From the result it is found that a self-repairable system is realizable and the system is useful for the run-time as well as fabrication-time reconfiguration because it requires no host computer to execute the reconfiguration algorithm and the reconfiguration time is very short.

As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the fault-free target logical system are described in the literature [1]-[5]. In this paper, we propose an efficient approximate method which can reconstruct the 1 1/2 track-switch mesh arrays with faulty PEs using hardware as well as software. A logical circuit added to each PE and a network connecting the circuits are used to decide spare PEs which compensate for faulty PEs. The hardware compexity of each circuit is much less than that of a PE where the size of each additional circuit is independent of array sizes and constant. By using the exclusive hardware scheme, a built-in self-reconfigurable system without using a host computer is realizable and the time for reconfiguring arrays becomes very short. The simulation result of the performance of the method shows that the reconstructing efficiency of our algorithm is a little less than those of the exaustive and Shigei's ones [6] and [7], but much better than that of the neural one [3]. We also compare the time complexities of reconstructions by hardware as well as software, and the hardware complexity in terms of the number of gates in the logical circuit added to each PE among the other methods.

The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

Various reconfiguration schemes against faults of mesh-connected processor arrays have been proposed. As one of them, the mesh-connected processor arrays model based on single-track switches was proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. Furthermore, the 2 track switch model [2] and the multiple track switch model [3] were proposed to enhance yields and reliabilities of arrays. However, in these models, Simplicity of the routing hardware is somewhat lost because multiple tracks are used for each row and column. In this paper, we present a builtin self-reconstruction approach for mesh-connected processor arrays which are partitioned into sub-arrays each using single-track switches. Spare PEs which are located on the boundaries of the sub-arrays compensate faulty PEs in these sub-arrays. First, we formulate a reconfigulation algorithm for partitioned mesh-arrays using a Hopfield-type neural network, and then its performance for reconfigulation in terms of survival rates and reliabilities of arrays and processing time are investigated by computer simulations. From the results, we can see that high reliabilites are achieved while processing time is a little and hardware overhead (links and switches) required for reconstruction is as same as that for the track switch model. Next, we present a hardware implementation of the neural algorithm so that a built-in self-reconfigurable scheme may be realized.