An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults

Tadayoshi HORITA; Itsuo TAKANAMI

An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults

Tadayoshi HORITA, Itsuo TAKANAMI

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The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

Publication: IEICE TRANSACTIONS on Information Vol.E80-D No.9 pp.879-885

Publication Date: 1997/09/25

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Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)

Category: Fault Tolerance

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Tadayoshi HORITA, Itsuo TAKANAMI, "An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults" in IEICE TRANSACTIONS on Information, vol. E80-D, no. 9, pp. 879-885, September 1997, doi: .
Abstract: The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_9_879/_p

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@ARTICLE{e80-d_9_879,
author={Tadayoshi HORITA, Itsuo TAKANAMI, },
journal={IEICE TRANSACTIONS on Information},
title={An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults},
year={1997},
volume={E80-D},
number={9},
pages={879-885},
abstract={The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults
T2 - IEICE TRANSACTIONS on Information
SP - 879
EP - 885
AU - Tadayoshi HORITA
AU - Itsuo TAKANAMI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1997
AB - The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.
ER -