The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and Horse-allocation) are introduced and compared.

The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

This paper proposes a new duplication redundancy technology, 2 Transistors for 1.5 Gates, that is capable of automatic defect tolerance, so making large, high-resolution, color TFT-LCD panel fabrication both easy and economical. This redundancy technology with automatic defect tolerant capability has a low hardware overhead and is very capable of compensating for open circuit defects in a large active-matrix panel. This technology was confirmed by fabricating a 9.5-inch color TFT-LCD panel with 640480 pixels(960960 dots). This panel showed excellent display performance and produced pictures without defects. The yield improvement effect of this technology was also confirmed by calculation based on the Boltzmann statistics model. Consequently, this technology is clearly seen to have a yield improvement effect equal to defect density reduction of about one order, compared to non redundancy. This technology drastically reduces dot and line defects, enabling fabrication of large, high-resolution, color TFT-LCD panels at a relatively low cost.