IEICE TRANSACTIONS on Communications
Multi-Stage Fiber Delay Line Buffer in Photonic Packet Switch for Asynchronously Arriving Variable-Length Packets
Summary :
We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E88-B No.1 pp.258-265
- Publication Date
- 2005/01/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietcom/e88-b.1.258
- Type of Manuscript
- PAPER
- Category
- Internet
Authors
Keyword
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Nobuo OGASHIWA, Hiroaki HARAI, Naoya WADA, Fumito KUBOTA, Yoichi SHINODA, "Multi-Stage Fiber Delay Line Buffer in Photonic Packet Switch for Asynchronously Arriving Variable-Length Packets" in IEICE TRANSACTIONS on Communications,
vol. E88-B, no. 1, pp. 258-265, January 2005, doi: 10.1093/ietcom/e88-b.1.258.
Abstract: We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.
URL: https://global.ieice.org/en_transactions/communications/10.1093/ietcom/e88-b.1.258/_p
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@ARTICLE{e88-b_1_258,
author={Nobuo OGASHIWA, Hiroaki HARAI, Naoya WADA, Fumito KUBOTA, Yoichi SHINODA, },
journal={IEICE TRANSACTIONS on Communications},
title={Multi-Stage Fiber Delay Line Buffer in Photonic Packet Switch for Asynchronously Arriving Variable-Length Packets},
year={2005},
volume={E88-B},
number={1},
pages={258-265},
abstract={We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.},
keywords={},
doi={10.1093/ietcom/e88-b.1.258},
ISSN={},
month={January},}
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TY - JOUR
TI - Multi-Stage Fiber Delay Line Buffer in Photonic Packet Switch for Asynchronously Arriving Variable-Length Packets
T2 - IEICE TRANSACTIONS on Communications
SP - 258
EP - 265
AU - Nobuo OGASHIWA
AU - Hiroaki HARAI
AU - Naoya WADA
AU - Fumito KUBOTA
AU - Yoichi SHINODA
PY - 2005
DO - 10.1093/ietcom/e88-b.1.258
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E88-B
IS - 1
JA - IEICE TRANSACTIONS on Communications
Y1 - January 2005
AB - We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.
ER -
English
