We propose a new label recognition system for photonic label routing network. Binary-coded labels in binary phase-shift-keying format are considered. The system consists of an optical waveguide circuit with tree-structure passive asymmetric X-junctions and time gates. The system uses self-routing propagation of an identifying bit by performing interference with address bits. The identifying bit is placed in advance of the address bits in the label. The identifying bit pulse is routed to the destination output port corresponding to the code of the address. The operation principle is described. It is shown that all the binary number codes can be recognized with this system. We discuss the feasibility of the system by evaluating its crosstalk. To reduce the crosstalk, an improved scheme is also presented. The label recognition operation with the optical waveguide device is verified by numerical simulation using the finite-difference beam propagation method.

We propose a new label recognition system for photonic label switching using self-routing of labels. Binary-coded labels in on-off keying format are considered. The system consists of an all-optical demultiplexer (DeMUX) and an address recognition unit (ARU) consisting of tree-structured switches. The system uses self-routing propagation of an indication bit controlled with address bits. The indication bit is placed in advance of the address bits in the label. In DeMUX, all-optical switches in a configuration of Mach-Zehnder interferometer with semiconductor optical amplifiers (SOA-MZI) are controlled by the indication bit pulse to separate each of the label bits. The indication bit pulse is routed to the destination output port corresponding to the code of the address in ARU. It is shown that all the binary number codes can be recognized with this system. The operation principle is verified by numerical simulation using coupled-mode theory and a rate equation. Moreover, the switching crosstalk is also evaluated.

We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an output buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced by its architecture and a packet scheduling algorithm. We compare the performances of these two packet switches by applying different packet scheduling algorithms. Through simulation experiments, we show that each architecture has a parameter region for achieving better performance. For the shared buffer type switch, we found that void space introduces unacceptable performance degradation when the traffic load is high. Accordingly, we propose a void space reduction method. Our simulation results show that our proposed method enables to the shared buffer type switch to outperform the output buffer type switch even under high traffic load conditions.

A rack-mounted prototype packet switch that makes use of wavelength-division-multiplexing (WDM) interconnect techniques has been developed. The switch has a maximum throughput of 320 Gbit/s. It features a WDM star-based switch architecture, an electrical control circuit layer and a broad-bandwidth optical WDM layer. The basic characteristics of the broad bandwidth WDM layer, such as level diagram, transmission characteristics, 32-wavelength-channel switching, and high-speed optical gating within a 1.6-ns guard time, are described. Experimental results demonstrated that the switch can perform practical self-routing switch operations, such as address-extraction, optical buffering, and filtering for packet speeds of up to 10 Gbit/s. The switch is promising for such applications as a terabit-per-second switching node in future WDM transport networks.

The application of photonic technologies to packet switching offers the potential of very large switch capacity in the terabit per second range. The merging of packet switching with photonic technologies opens up the possibility of packet switching in transparent photonic media, in which packets remain in optical form without undergoing optoelectronic conversion. This paper reviews recent work on photonic packet switching. Different approaches to photonic packet switching and key design issues are discussed.

The application of photonic technologies to packet switching offers the potential of very large switch capacity in the terabit per second range. The merging of packet switching with photonic technologies opens up the possibility of packet switching in transparent photonic media, in which packets remain in optical form without undergoing optoelectronic conversion. This paper reviews recent work on photonic packet switching. Different approaches to photonic packet switching and key design issues are discussed.