Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation

Jung-Yeol OH; Myoung-Seob LIM

doi:10.1093/ietcom/e89-b.4.1425

Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation

Jung-Yeol OH, Myoung-Seob LIM

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This paper proposes the new radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.

Publication: IEICE TRANSACTIONS on Communications Vol.E89-B No.4 pp.1425-1429

Publication Date: 2006/04/01

Publicized

Online ISSN: 1745-1345

DOI: 10.1093/ietcom/e89-b.4.1425

Type of Manuscript: LETTER

Category: Devices/Circuits for Communications

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Jung-Yeol OH, Myoung-Seob LIM, "Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation" in IEICE TRANSACTIONS on Communications, vol. E89-B, no. 4, pp. 1425-1429, April 2006, doi: 10.1093/ietcom/e89-b.4.1425.
Abstract: This paper proposes the new radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.
URL: https://global.ieice.org/en_transactions/communications/10.1093/ietcom/e89-b.4.1425/_p

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@ARTICLE{e89-b_4_1425,
author={Jung-Yeol OH, Myoung-Seob LIM, },
journal={IEICE TRANSACTIONS on Communications},
title={Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation},
year={2006},
volume={E89-B},
number={4},
pages={1425-1429},
abstract={This paper proposes the new radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.},
keywords={},
doi={10.1093/ietcom/e89-b.4.1425},
ISSN={1745-1345},
month={April},}

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TY - JOUR
TI - Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation
T2 - IEICE TRANSACTIONS on Communications
SP - 1425
EP - 1429
AU - Jung-Yeol OH
AU - Myoung-Seob LIM
PY - 2006
DO - 10.1093/ietcom/e89-b.4.1425
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E89-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2006
AB - This paper proposes the new radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.
ER -